Patents by Inventor Hatsuhide Igarashi

Hatsuhide Igarashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060022803
    Abstract: A semiconductor device, comprises a receive circuit for generating receive data from received radio signals, a power supply voltage generation circuit for generating power supply voltage based on the received radio signals, a control circuit for performing logical processing based on the received data, a transmission circuit for generating radio signals including transmission data and transmitting the radio signals via an antenna and an oscillation circuit, which is operated using the power supply voltage generated by the power supply voltage generation circuit, for generating a predetermined frequency of clocks.
    Type: Application
    Filed: July 28, 2005
    Publication date: February 2, 2006
    Inventors: Kazuhiro Akiyama, Hatsuhide Igarashi, Seiichi Okamoto, Toshiyuki Miyashita, Kazumi Seki, Tatsuya Uchino, Shigeki Kajimoto
  • Publication number: 20060022058
    Abstract: A semiconductor device for an IC tag comprises a receive unit for demodulating receive data from a received RF signal and a signal processing unit for detecting a command comprising data signals from the receive data demodulated by the receive unit and executing processing based on the command, wherein the signal processing unit has a command acceptance mode for detecting the command from the receive data and a command execution mode for executing the command, and cancels the data signal when the data signal is detected from the receive data in the command execution mode.
    Type: Application
    Filed: July 28, 2005
    Publication date: February 2, 2006
    Inventors: Kazuhiro Akiyama, Hatsuhide Igarashi, Seiichi Okamoto, Toshiyuki Miyashita, Kazumi Seki, Tatsuya Uchino, Shigeki Kajimoto
  • Patent number: 5708372
    Abstract: In a semiconductor device in which power is supplied from an external power supply system, a first power supply system is connected to first terminals of power supply and ground and a digital inner circuit. The inner circuit includes a clock signal generating circuit, a driver for the clock signal, and circuits operating in response to the clock signal. A second power supply system is connected to second terminals of power supply and ground, the input terminal, the output terminal, and a digital interface circuit. The second power supply system is independent of the first power supply system. The interface circuit includes a MOS transistor for pulling up or down the input terminal and an output circuit which includes a MOS transistor driving an output terminal. The first power supply system is separated from the second power supply system, and the inner circuit is connected to the interface circuit through only signal lines.
    Type: Grant
    Filed: June 5, 1996
    Date of Patent: January 13, 1998
    Assignee: NEC Corporation
    Inventors: Hatsuhide Igarashi, Shigeru Takayama, Yoshihiro Matsuura, Hatsuhiro Nagaishi
  • Patent number: 4656491
    Abstract: A protection circuit is composed of first and second regions formed in a semiconductor substrate so as to be operable as distributed transistors which have a large current capacity as a whole. Compared with the concentrated transistor used in the prior art, a much greater degree of protection is provided.
    Type: Grant
    Filed: November 17, 1983
    Date of Patent: April 7, 1987
    Assignee: NEC Corporation
    Inventor: Hatsuhide Igarashi
  • Patent number: 4488061
    Abstract: A drive circuit which can drive an IGFET in a non-saturated region over a long period time without reduction in level is disclosed. The drive circuit comprises a series circuit of a plurality of directional elements connected between a power supply terminal and an output terminal, a plurality of control terminals receiving repetitional signals and a plurality of capacitors coupled between the control terminals and intermediate junctions of the series circuit.
    Type: Grant
    Filed: February 24, 1982
    Date of Patent: December 11, 1984
    Assignee: Nippon Electric Co., Ltd.
    Inventors: Tojiro Mukawa, Hatsuhide Igarashi
  • Patent number: 4321562
    Abstract: A single-stage inverter forming a closed loop together with a crystal resonator fails to provide sufficient gain and hence, power consumption becomes high during stable oscillation. If inverters are coupled together in a three-stage cascade-connection, on the other hand, the gain becomes excessively high and undesired high frequency oscillation takes place at the start of oscillation. This invention provides a crystal oscillator circuit which, in order to solve these problems, uses a single-stage inverter to form a closed loop with a crystal resonator at the start of oscillation and uses three-stage inverters cascade-connected with each other during stable oscillation.
    Type: Grant
    Filed: January 9, 1980
    Date of Patent: March 23, 1982
    Assignee: Nippon Electric Co., Ltd.
    Inventor: Hatsuhide Igarashi