Patents by Inventor Hau Ng
Hau Ng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11939423Abstract: A breathable biodegradable volatile corrosion inhibitor polyester composition comprises one or more biodegradable homopolymer polyesters and/or one or more biodegradable random copolymer polyesters, one or more volatile corrosion inhibitors (VCI), and one or more fillers wherein said composition has a higher water-vapor transmission rate than polyethylene.Type: GrantFiled: June 30, 2020Date of Patent: March 26, 2024Assignee: Northern Technologies International CorporationInventors: Mahin Shahlari, Ik-Hau Ng
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Publication number: 20240047266Abstract: A method of forming a protective layer utilized in a silicon remove process includes bonding a first wafer to a second wafer, wherein the first wafer comprises a first silicon substrate with a first device structure disposed thereon and the second wafer comprises a second silicon substrate with a second device structure disposed thereon. After that, a first trim process is performed to thin laterally an edge of the first wafer and an edge of the second device structure. After the first trim process, a protective layer is formed to cover a back side of the second silicon substrate. After forming the protective layer, a silicon remove process is performed to remove only the first silicon substrate.Type: ApplicationFiled: August 4, 2022Publication date: February 8, 2024Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chia-Liang Liao, Chee Hau Ng, Ching-Yang Wen, Purakh Raj Verma
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Publication number: 20240038832Abstract: A semiconductor device includes a substrate, a high-Q capacitor, an ultra high density capacitor, and an interconnection. At least one trench is formed in the substrate. The high-Q capacitor is disposed on a surface of the substrate, and includes a bottom electrode, an upper electrode located on the bottom electrode, and a first dielectric layer located between the upper and bottom electrodes. The ultra high density capacitor is disposed on the trench of the substrate, and includes a first electrode conformally deposited in the trench, a second electrode located on the first electrode, and a second dielectric layer located between the first and second electrodes. The interconnection connects one of the upper electrode and the bottom electrode to one of the first electrode and the second electrode, and connects the other of the upper electrode and the bottom electrode to the other of the first electrode and the second electrode.Type: ApplicationFiled: August 21, 2022Publication date: February 1, 2024Applicant: United Microelectronics Corp.Inventors: Purakh Raj Verma, Ching-Yang Wen, Chee-Hau Ng, Chin-Wei Ho
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Publication number: 20230268246Abstract: A semiconductor structure includes a glass substrate and a device structure. The glass substrate includes a glass layer, a heat dissipation layer and a silicon nitride layer stacked from bottom to top. The device structure includes at least one semiconductor device integrated in a device layer situated over the silicon nitride layer of the glass substrate. Or, the glass substrate includes a glass layer and a silicon nitride layer stacked from bottom to top. The device structure includes at least one semiconductor device integrated in a device layer, and a heat dissipation layer is stacked on the device layer, wherein the heat dissipation layer is bonded with the silicon nitride layer of the glass substrate. The present invention also provides a method of wafer bonding for manufacturing said semiconductor structure.Type: ApplicationFiled: April 18, 2023Publication date: August 24, 2023Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chia-Liang Liao, Purakh Raj Verma, Ching-Yang Wen, Chee Hau Ng
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Patent number: 11670567Abstract: A semiconductor structure includes a glass substrate and a device wafer. The glass substrate includes a glass layer, a heat dissipation layer and a silicon nitride layer stacked from bottom to top. The device wafer includes at least one semiconductor device integrated in a device layer situated over the silicon nitride layer of the glass substrate. Or, the glass substrate includes a glass layer and a silicon nitride layer stacked from bottom to top. The device wafer includes at least one semiconductor device integrated in a device layer, and a heat dissipation layer is stacked on the device layer, wherein the heat dissipation layer is bonded with the silicon nitride layer of the glass substrate. The present invention also provides a method of wafer bonding for manufacturing said semiconductor structure.Type: GrantFiled: July 9, 2020Date of Patent: June 6, 2023Assignee: UNITED MICROELECTRONICS CORP.Inventors: Chia-Liang Liao, Purakh Raj Verma, Ching-Yang Wen, Chee Hau Ng
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Patent number: 11398548Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an insulating layer, a semiconductor layer, a plurality of isolation structures, a transistor, a first contact, a plurality of silicide layers, and a protective layer. The semiconductor layer is disposed on a front side of the insulating layer. The plurality of isolation structures are disposed in the semiconductor layer. The transistor is disposed on the semiconductor layer. The first contact is disposed beside the transistor and passes through one of the plurality of isolation structures and the insulating layer therebelow. The plurality of silicide layers are respectively disposed on a bottom surface of the first contact and disposed on a source, a drain, and a gate of the transistor. The protective layer is disposed between the first contact and the insulating layer.Type: GrantFiled: December 16, 2020Date of Patent: July 26, 2022Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wen-Shen Li, Ching-Yang Wen, Purakh Raj Verma, Xingxing Chen, Chee-Hau Ng
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Publication number: 20220185953Abstract: A breathable biodegradable volatile corrosion inhibitor polyester composition comprises one or more biodegradable homopolymer polyesters and/or one or more biodegradable random copolymer polyesters, one or more volatile corrosion inhibitors (VCI), and one or more fillers wherein said composition has a higher water-vapor transmission rate than polyethylene.Type: ApplicationFiled: June 30, 2020Publication date: June 16, 2022Inventors: Mahin Shahlari, Ik-Hau Ng
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Publication number: 20220013430Abstract: A semiconductor structure includes a glass substrate and a device wafer. The glass substrate includes a glass layer, a heat dissipation layer and a silicon nitride layer stacked from bottom to top. The device wafer includes at least one semiconductor device integrated in a device layer situated over the silicon nitride layer of the glass substrate. Or, the glass substrate includes a glass layer and a silicon nitride layer stacked from bottom to top. The device wafer includes at least one semiconductor device integrated in a device layer, and a heat dissipation layer is stacked on the device layer, wherein the heat dissipation layer is bonded with the silicon nitride layer of the glass substrate. The present invention also provides a method of wafer bonding for manufacturing said semiconductor structure.Type: ApplicationFiled: July 9, 2020Publication date: January 13, 2022Inventors: Chia-Liang Liao, Purakh Raj Verma, Ching-Yang Wen, Chee Hau Ng
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Publication number: 20210104602Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an insulating layer, a semiconductor layer, a plurality of isolation structures, a transistor, a first contact, a plurality of silicide layers, and a protective layer. The semiconductor layer is disposed on a front side of the insulating layer. The plurality of isolation structures are disposed in the semiconductor layer. The transistor is disposed on the semiconductor layer. The first contact is disposed beside the transistor and passes through one of the plurality of isolation structures and the insulating layer therebelow. The plurality of silicide layers are respectively disposed on a bottom surface of the first contact and disposed on a source, a drain, and a gate of the transistor. The protective layer is disposed between the first contact and the insulating layer.Type: ApplicationFiled: December 16, 2020Publication date: April 8, 2021Applicant: United Microelectronics Corp.Inventors: Wen-Shen Li, Ching-Yang Wen, Purakh Raj Verma, Xingxing Chen, Chee-Hau Ng
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Patent number: 10903314Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an insulating layer, a semiconductor layer, a plurality of isolation structures, a transistor, a first contact, a plurality of silicide layers, and a protective layer. The semiconductor layer is disposed on a front side of the insulating layer. The plurality of isolation structures are disposed in the semiconductor layer. The transistor is disposed on the semiconductor layer. The first contact is disposed beside the transistor and passes through one of the plurality of isolation structures and the insulating layer therebelow. The plurality of silicide layers are respectively disposed on a bottom surface of the first contact and disposed on a source, a drain, and a gate of the transistor. The protective layer is disposed between the first contact and the insulating layer.Type: GrantFiled: June 25, 2018Date of Patent: January 26, 2021Assignee: UNITED MICROELECTRONICS CORP.Inventors: Wen-Shen Li, Ching-Yang Wen, Purakh Raj Verma, Xingxing Chen, Chee-Hau Ng
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Patent number: 10622253Abstract: A manufacturing method of a semiconductor device including the following steps is provided. A substrate having a device structure and a first interconnection structure on a front side is provided. A first annealing process is performed in an atmosphere of pure hydrogen at a first temperature. A second interconnection structure is formed on a back side of the substrate. A second annealing process is performed in an atmosphere of gas mixture including hydrogen at a second temperature.Type: GrantFiled: June 12, 2018Date of Patent: April 14, 2020Assignee: UNITED MICROELECTRONICS CORP.Inventors: Li-Da Huang, Wei-Hui Gao, Chien-Kee Pang, Wen-Bo Ding, Sheng Zhang, Wen-Shen Li, Chee-Hau Ng, Xiaoyuan Zhi
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Publication number: 20190378757Abstract: A manufacturing method of a semiconductor device including the following steps is provided. A substrate having a device structure and a first interconnection structure on a front side is provided. A first annealing process is performed in an atmosphere of pure hydrogen at a first temperature. A second interconnection structure is formed on a back side of the substrate. A second annealing process is performed in an atmosphere of gas mixture including hydrogen at a second temperature.Type: ApplicationFiled: June 12, 2018Publication date: December 12, 2019Applicant: United Microelectronics Corp.Inventors: Li-Da Huang, Wei-Hui Gao, Chien-Kee Pang, Wen-Bo Ding, Sheng Zhang, Wen-Shen Li, Chee-Hau Ng, Xiaoyuan Zhi
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Publication number: 20190355812Abstract: A semiconductor device and a method for manufacturing the semiconductor device are provided. The semiconductor device includes an insulating layer, a semiconductor layer, a plurality of isolation structures, a transistor, a first contact, a plurality of silicide layers, and a protective layer. The semiconductor layer is disposed on a front side of the insulating layer. The plurality of isolation structures are disposed in the semiconductor layer. The transistor is disposed on the semiconductor layer. The first contact is disposed beside the transistor and passes through one of the plurality of isolation structures and the insulating layer therebelow. The plurality of silicide layers are respectively disposed on a bottom surface of the first contact and disposed on a source, a drain, and a gate of the transistor. The protective layer is disposed between the first contact and the insulating layer.Type: ApplicationFiled: June 25, 2018Publication date: November 21, 2019Applicant: United Microelectronics Corp.Inventors: Wen-Shen Li, Ching-Yang Wen, Purakh Raj Verma, Xingxing Chen, Chee-Hau Ng
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Patent number: 9496187Abstract: A multiple-sample-holder polishing setup for cross-section sample preparation and a method of making a device using the same are presented. The multiple-sample-holder polishing setup includes a frame. The frame has a hollow center, one or more long and short rods and a recess for accommodating a polishing head. The setup includes one or more sample holders. The sample holder is to be attached to the one or more long and short rods of the frame. A paddle is affixed to each sample holder. A sample is attached to the paddle. The sample is coated with a thin epoxy layer prior to polishing thereby allowing for easy inspection for site of interests as well as quick material removal.Type: GrantFiled: November 20, 2013Date of Patent: November 15, 2016Assignee: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Tsu Hau Ng, Zhihong Mai, Mohammed Khalid Bin Dawood, Pik Kee Tan, Yamin Huang, Jeffrey Chor-Keung Lam
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Patent number: 9128117Abstract: A method for sharpening a nanotip involving a laser-enhanced chemical etching is provided. The method includes immersing a nanotip in an etchant solution. The nanotip includes a base and an apex, the apex having a diameter smaller than a diameter of the base. The method also includes irradiating the nanotip with laser fluence to establish a temperature gradient in the nanotip along a direction from the apex to the base of the nanotip such that the apex and base are etched at different rates.Type: GrantFiled: December 4, 2013Date of Patent: September 8, 2015Assignee: GLOBALFOUNDRIES SINGAPORE PTE. LTD.Inventors: ZhiHong Mai, Jeffrey C. Lam, Mohammed Khalid Bin Dawood, Tsu Hau Ng
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Publication number: 20150140688Abstract: A multiple-sample-holder polishing setup for cross-section sample preparation and a method of making a device using the same are presented. The multiple-sample-holder polishing setup includes a frame. The frame has a hollow center, one or more long and short rods and a recess for accommodating a polishing head. The setup includes one or more sample holders. The sample holder is to be attached to the one or more long and short rods of the frame. A paddle is affixed to each sample holder. A sample is attached to the paddle. The sample is coated with a thin epoxy layer prior to polishing thereby allowing for easy inspection for site of interests as well as quick material removal.Type: ApplicationFiled: November 20, 2013Publication date: May 21, 2015Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: Tsu Hau NG, Zhihong MAI, Mohammed Khalid Bin DAWOOD, Pik Kee TAN, Yamin HUANG, Jeffrey Chor-Keung LAM
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Publication number: 20140242805Abstract: A method for sharpening a nanotip involving a laser-enhanced chemical etching is provided. The method includes immersing a nanotip in an etchant solution. The nanotip includes a base and an apex, the apex having a diameter smaller than a diameter of the base. The method also includes irradiating the nanotip with laser fluence to establish a temperature gradient in the nanotip along a direction from the apex to the base of the nanotip such that the apex and base are etched at different rates.Type: ApplicationFiled: December 4, 2013Publication date: August 28, 2014Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.Inventors: ZhiHong MAI, Jeffrey C. LAM, Mohammed Khalid BIN DAWOOD, Tsu Hau NG
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Patent number: 8686757Abstract: An apparatus and a method are provided for selectively enabling and disabling a squelch circuit in a Serial Advanced Technology Attachment (SATA) host or SATA device while maintaining proper operation of the host and device. An apparatus and method are provided which allow the squelch circuit to be selectively enabled and disabled across SATA power states (PHY Ready, Partial, and Slumber) and in Advanced Host Controller Interface (AHCI) Listen mode.Type: GrantFiled: March 19, 2012Date of Patent: April 1, 2014Assignee: Intel CorporationInventors: Jien-Hau Ng, Tea M. Lee
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Publication number: 20120280719Abstract: An apparatus and a method are provided for selectively enabling and disabling a squelch circuit in a Serial Advanced Technology Attachment (SATA) host or SATA device while maintaining proper operation of the host and device. An apparatus and method are provided which allow the squelch circuit to be selectively enabled and disabled across SATA power states (PHY Ready, Partial, and Slumber) and in Advanced Host Controller Interface (AHCI) Listen mode.Type: ApplicationFiled: March 19, 2012Publication date: November 8, 2012Inventors: Jien-Hau Ng, Tea M. Lee
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Patent number: 8138803Abstract: An apparatus and a method are provided for selectively enabling and disabling a squelch circuit in a Serial Advanced Technology Attachment (SATA) host or SATA device while maintaining proper operation of the host and device. An apparatus and method are provided which allow the squelch circuit to be selectively enabled and disabled across SATA power states (PHY Ready, Partial, and Slumber) and in Advanced Host Controller Interface (AHCI) Listen mode.Type: GrantFiled: September 26, 2007Date of Patent: March 20, 2012Assignee: Intel CorporationInventors: Jien-Hau Ng, Tea M. Lee