Patents by Inventor Hau Wang
Hau Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240171180Abstract: A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.Type: ApplicationFiled: February 1, 2024Publication date: May 23, 2024Inventors: GUO-HAU LEE, HUAI-TE WANG, CHENG-LIANG HUNG
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Publication number: 20240145344Abstract: A via structure, a semiconductor structure, and methods for forming the via structure and the semiconductor structure are presented. A via structure includes a first conductive portion through an interconnect structure, a second conductive portion through a substrate and in contact with the first conductive portion, and a liner layer. The liner layer is between the first conductive portion and the interconnect structure, and between the second conductive portion and the substrate. The liner layer includes a portion extending parallel to a surface of the substrate.Type: ApplicationFiled: February 22, 2023Publication date: May 2, 2024Inventors: Tsung-Chieh Hsiao, Liang-Wei Wang, Dian-Hau Chen
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Publication number: 20240145435Abstract: Some implementations described herein include systems and techniques for fabricating a multi-dimension through silicon via structure in a three-dimensional integrated circuit device. The multi-dimension through silicon via structure includes a first columnar structure having a first width and a second columnar structure including a second width that is greater relative to the first width. The first columnar structure may include a low electrical capacitance and be configured for electrical signaling within the three-dimensional integrated circuit device. The second columnar structure may be configured to provide power to integrated circuitry of the three-dimensional integrated circuit device and also be configured to conduct heat through the three-dimensional integrated circuit device for thermal management of the three-dimensional integrated circuit device. Additionally, a pattern including the second columnar structure may be used for alignment purposes.Type: ApplicationFiled: April 26, 2023Publication date: May 2, 2024Inventors: Ke-Gang WEN, Tsung-Chieh HSIAO, Liang-Wei WANG, Dian-Hau CHEN
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Publication number: 20240120257Abstract: An integrated circuit (IC) device includes a substrate. The IC device includes a multi-layer interconnect structure disposed over a first side of the substrate. The multi-layer interconnect structure includes a plurality of metal layers. The IC device includes a first portion of a through-substrate via (TSV) disposed over the first side of the substrate. The first portion of the TSV includes a plurality of conductive components belonging to the plurality of metal layers of the multi-layer interconnect structure. The IC device includes a second portion of the TSV that extends vertically through the substrate from the first side to a second side opposite the first side. The second portion of the TSV is electrically coupled to the first portion of the TSV.Type: ApplicationFiled: March 30, 2023Publication date: April 11, 2024Inventors: Tsung-Chieh Hsiao, Ke-Gang Wen, Liang-Wei Wang, Dian-Hau Chen
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Publication number: 20240110292Abstract: The present invention provides, in part, methods and processes for the production of lithium superoxide (LiO2) which is free of other lithium-oxygen compounds, as well as compositions and electrochemical cells comprising lithium superoxide (e.g., lithium superoxide that is free of other lithium-oxygen compounds).Type: ApplicationFiled: September 22, 2022Publication date: April 4, 2024Applicant: UCHICAGO ARGONNE, LLCInventors: Larry A. Curtiss, Hsien-Hau Wang, Khalil Amine, Samuel Plunkett
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Patent number: 11950432Abstract: A semiconductor package includes a first semiconductor device and a second semiconductor device. The first semiconductor device includes a first semiconductor substrate, a first bonding structure and a memory cell. The second semiconductor device is stacked over the first semiconductor device. The second semiconductor device includes a second semiconductor substrate, a second bonding structure in a second dielectric layer and a peripheral circuit between the second semiconductor substrate and the second bonding structure. The first bonding structure and the second bonding structure are bonded and disposed between the memory cell and the peripheral circuit, and the memory cell and the peripheral circuit are electrically connected through the first bonding structure and the second bonding structure.Type: GrantFiled: June 29, 2021Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiang-Ku Shen, Ku-Feng Lin, Liang-Wei Wang, Dian-Hau Chen
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Patent number: 11948798Abstract: A method for manufacturing an integrated circuit includes patterning a plurality of photomask layers over a substrate, partially backfilling the patterned plurality of photomask layers with a first material using atomic layer deposition, completely backfilling the patterned plurality of photomask layers with a second material using atomic layer deposition, removing the plurality of photomask layers to form a masking structure comprising at least one of the first and second materials, and transferring a pattern formed by the masking structure to the substrate and removing the masking structure. The first material includes a silicon dioxide, silicon carbide, or carbon material, and the second material includes a metal oxide or metal nitride material.Type: GrantFiled: July 16, 2021Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ching-Yu Chang, Jung-Hau Shiu, Jen Hung Wang, Tze-Liang Lee
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Patent number: 11937515Abstract: Semiconductor device and methods of forming the same are provided. A semiconductor device according to one embodiment includes a dielectric layer including a top surface, a plurality of magneto-resistive memory cells disposed in the dielectric layer and including top electrodes, a first etch stop layer disposed over the dielectric layer, a common electrode extending through the first etch stop layer to be in direct contact with the top electrodes, and a second etch stop layer disposed on the first etch stop layer and the common electrode. Top surfaces of the top electrodes are coplanar with the top surface of the dielectric layer.Type: GrantFiled: August 9, 2022Date of Patent: March 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chih-Fan Huang, Hsiang-Ku Shen, Liang-Wei Wang, Chen-Chiu Huang, Dian-Hau Chen, Yen-Ming Chen
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Patent number: 11936388Abstract: A clock and data recovery circuit includes a sampling circuit, a phase detector, a first processing circuit, a second processing circuit and an oscillator circuit. The sampling circuit is configured to sample input data according to an output clock, and generate a sampling result. The phase detector is configured to generate a detection result according to the sampling result. The first processing circuit is configured to process the sampling result to generate a first digital code. The second processing circuit is configured to accumulate a portion of the first digital code to generate a second digital code. A rate of change of a code value of the second digital code is slower than a rate of change of a code value of the first digital code. The oscillator circuit is configured to generate the output clock according to the detection result, the first digital code and the second digital code.Type: GrantFiled: December 27, 2022Date of Patent: March 19, 2024Assignee: M31 TECHNOLOGY CORPORATIONInventors: Guo-Hau Lee, Huai-Te Wang, Cheng-Liang Hung
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Publication number: 20240071956Abstract: Semiconductor structures and methods for forming the same are provided. A method according to the present disclosure includes forming active regions on a substrate, forming an interconnect structure over the active regions, the interconnect structure including a plurality of dielectric layers and a guard ring disposed within the dielectric layers, etching an opening through the interconnect structure and at least a first portion of the active regions, the opening extending into the substrate, and forming a via structure within the opening. The via structure is surrounded by the guard ring when viewed along a direction perpendicular to a top surface of the substrate.Type: ApplicationFiled: April 21, 2023Publication date: February 29, 2024Inventors: Chih Hsin YANG, Yen Lian LAI, Dian-Hau CHEN, Mao-Nan WANG
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Patent number: 11679565Abstract: An additive manufacturing (AM) method includes using an AM tool to fabricate a plurality of workpiece products; measuring qualities of the first workpiece products respectively; performing a temperature measurement on each of the melt pools on the powder bed during a fabrication of each of the workpiece products; performing photography on each of the melt pools on the powder bed during the fabrication of each of the workpiece products; extracting a length and a width of each of the melt pools; performing a melt-pool feature processing operation; building a conjecture model by using a plurality of sets of first process data and the actual metrology values of the first workpiece products in accordance with a prediction algorithm; and predicting a virtual metrology value of the second workpiece product by using the conjecture model based on a set of second process data.Type: GrantFiled: June 6, 2022Date of Patent: June 20, 2023Assignee: NATIONAL CHENG KUNG UNIVERSITYInventors: Haw-Ching Yang, Yu-Lung Lo, Hung-Chang Hsiao, Shyh-Hau Wang, Min-Chun Hu, Chih-Hung Huang, Fan-Tien Cheng
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Patent number: 11673339Abstract: An additive manufacturing (AM) method includes using an AM tool to fabricate a plurality of workpiece products; measuring qualities of the first workpiece products respectively; performing a temperature measurement on each of the melt pools on the powder bed; performing photography on each of the melt pools on the powder bed; extracting a length and a width of each of the melt pools; performing a melt-pool feature processing operation; first converting each of the workspace images to a gray level co-occurrence matrix (GLCM); building a conjecture model by using a plurality of sets of first process data and the actual metrology values of the first workpiece products in accordance with a prediction algorithm; and predicting a virtual metrology value of the second workpiece product by using the conjecture model based on a set of second process data.Type: GrantFiled: June 17, 2022Date of Patent: June 13, 2023Assignee: NATIONAL CHENG KUNG UNIVERSITYInventors: Haw-Ching Yang, Yu-Lung Lo, Hung-Chang Hsiao, Shyh-Hau Wang, Min-Chun Hu, Chih-Hung Huang, Fan-Tien Cheng
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Patent number: 11658291Abstract: An electrochemical device includes a lithium anode having a red poly(benzonitrile) coating covering at least a portion of the anode; a separator and an air cathode comprising reduced graphene oxide over gas diffusion layer; and an electrolyte comprising an ether solvent, benzonitrile, and a lithium salt.Type: GrantFiled: July 28, 2020Date of Patent: May 23, 2023Assignee: UChicago Argonne, LLCInventors: Hsien-Hau Wang, Ritesh Jagatramka, Samuel Plunkett, Larry A. Curtiss, Khalil Amine
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Publication number: 20230098823Abstract: A steering joint comprises a first tubular member and a second tubular member. The first tubular member and the second tubular member include a plurality of cuts to facilitate bending. One end of the first tubular member has an accommodation portion for accommodating an endoscopic image module, and the other end has a first joint portion. One end of the second tubular member has a second joint portion which is joined to the first joint portion of the first tubular member. The tubular member of the steering joint is easy to injection mold and can reduce the accumulated tolerance. An endoscope including the abovementioned steering joint is also disclosed.Type: ApplicationFiled: September 8, 2022Publication date: March 30, 2023Inventors: CHU-MING CHENG, CHIA-JUNG LEE, YUEH-YING FAN, YI-MING TAI, CHUNG-HAU WANG
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Publication number: 20220314552Abstract: An additive manufacturing (AM) method includes using an AM tool to fabricate a plurality of workpiece products; measuring qualities of the first workpiece products respectively; performing a temperature measurement on each of the melt pools on the powder bed; performing photography on each of the melt pools on the powder bed; extracting a length and a width of each of the melt pools; performing a melt-pool feature processing operation; first converting each of the workspace images to a gray level co-occurrence matrix (GLCM); building a conjecture model by using a plurality of sets of first process data and the actual metrology values of the first workpiece products in accordance with a prediction algorithm; and predicting a virtual metrology value of the second workpiece product by using the conjecture model based on a set of second process data.Type: ApplicationFiled: June 17, 2022Publication date: October 6, 2022Inventors: Haw-Ching YANG, Yu-Lung LO, Hung-Chang HSIAO, Shyh-Hau WANG, Min-Chun HU, Chih-Hung HUANG, Fan-Tien CHENG
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Publication number: 20220297383Abstract: An additive manufacturing (AM) method includes using an AM tool to fabricate a plurality of workpiece products; measuring qualities of the first workpiece products respectively; performing a temperature measurement on each of the melt pools on the powder bed during a fabrication of each of the workpiece products; performing photography on each of the melt pools on the powder bed during the fabrication of each of the workpiece products; extracting a length and a width of each of the melt pools; performing a melt-pool feature processing operation; building a conjecture model by using a plurality of sets of first process data and the actual metrology values of the first workpiece products in accordance with a prediction algorithm; and predicting a virtual metrology value of the second workpiece product by using the conjecture model based on a set of second process data.Type: ApplicationFiled: June 6, 2022Publication date: September 22, 2022Inventors: Haw-Ching Yang, Yu-Lung Lo, Hung-Chang Hsiao, Shyh-Hau Wang, Min-Chun Hu, Chih-Hung Huang, Fan-Tien Cheng
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Patent number: 11383446Abstract: An additive manufacturing (AM) system, an AM method, and an AM feature extraction method are provided. The AM system includes an AM tool, a product metrology system, an in-situ metrology system, a virtual metrology (VM) system, a compensator, a track planner, a controller, a simulator and an augmented reality (AR) device. The simulator is used to find feasible parameter ranges, while the AR device is used to support operations and maintenance of the AM tool. The product metrology system, the in-situ metrology system and the VM system are integrated to estimate the variation of material on a powder bed of the AM tool. The compensator is used for compensating the process variation by adjusting process parameters. The product metrology system is used to measure the quality of products. The in-situ metrology system is used to collect features of melt pools on the powder bed.Type: GrantFiled: October 2, 2019Date of Patent: July 12, 2022Assignee: NATIONAL CHENG KUNG UNIVERSITYInventors: Haw-Ching Yang, Yu-Lung Lo, Hung-Chang Hsiao, Shyh-Hau Wang, Min-Chun Hu, Chih-Hung Huang, Fan-Tien Cheng
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Patent number: 11383450Abstract: An additive manufacturing (AM) system, an AM method, and an AM feature extraction method are provided. The AM system includes an AM tool, a product metrology system, an in-situ metrology system, a virtual metrology (VM) system, a compensator, a track planner, a controller, a simulator and an augmented reality (AR) device. The simulator is used to find feasible parameter ranges, while the AR device is used to support operations and maintenance of the AM tool. The product metrology system, the in-situ metrology system and the VM system are integrated to estimate the variation of material on a powder bed of the AM tool. The compensator is used for compensating the process variation by adjusting process parameters. The product metrology system is used to measure the quality of products. The in-situ metrology system is used to collect features of melt pools on the powder bed.Type: GrantFiled: April 22, 2020Date of Patent: July 12, 2022Assignee: NATIONAL CHENG KUNG UNIVERSITYInventors: Haw-Ching Yang, Yu-Lung Lo, Hung-Chang Hsiao, Shyh-Hau Wang, Min-Chun Hu, Chih-Hung Huang, Fan-Tien Cheng
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Publication number: 20220037646Abstract: An electrochemical device includes a lithium anode having a red poly(benzonitrile) coating covering at least a portion of the anode; a separator and an air cathode comprising reduced graphene oxide over gas diffusion layer; and an electrolyte comprising an ether solvent, benzonitrile, and a lithium salt.Type: ApplicationFiled: July 28, 2020Publication date: February 3, 2022Inventors: Hsien-Hau Wang, Ritesh Jagatramka, Samuel Plunkett, Larry A. Curtiss, Khalil Amine
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Publication number: 20200247064Abstract: An additive manufacturing (AM) system, an AM method, and an AM feature extraction method are provided. The AM system includes an AM tool, a product metrology system, an in-situ metrology system, a virtual metrology (VM) system, a compensator, a track planner, a controller, a simulator and an augmented reality (AR) device. The simulator is used to find feasible parameter ranges, while the AR device is used to support operations and maintenance of the AM tool. The product metrology system, the in-situ metrology system and the VM system are integrated to estimate the variation of material on a powder bed of the AM tool. The compensator is used for compensating the process variation by adjusting process parameters. The product metrology system is used to measure the quality of products. The in-situ metrology system is used to collect features of melt pools on the powder bed.Type: ApplicationFiled: April 22, 2020Publication date: August 6, 2020Inventors: Haw-Ching YANG, Yu-Lung LO, Hung-Chang HSIAO, Shyh-Hau WANG, Min-Chun HU, Chih-Hung HUANG, Fan-Tien CHENG