Patents by Inventor Haw-Jyh Liaw
Haw-Jyh Liaw has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10782344Abstract: A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.Type: GrantFiled: April 19, 2018Date of Patent: September 22, 2020Assignee: Rambus Inc.Inventors: Haw-Jyh Liaw, Xingchao Yuan, Mark A. Horowitz
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Publication number: 20180335477Abstract: A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.Type: ApplicationFiled: April 19, 2018Publication date: November 22, 2018Inventors: Haw-Jyh Liaw, Xingchao Yuan, Mark A. Horowitz
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Patent number: 9977076Abstract: A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.Type: GrantFiled: December 22, 2016Date of Patent: May 22, 2018Assignee: Rambus Inc.Inventors: Haw-Jyh Liaw, Xingchao Yuan, Mark A. Horowitz
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Publication number: 20170199242Abstract: A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.Type: ApplicationFiled: December 22, 2016Publication date: July 13, 2017Inventors: Haw-Jyh Liaw, Xingchao Yuan, Mark A. Horowitz
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Patent number: 9562934Abstract: A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.Type: GrantFiled: June 18, 2013Date of Patent: February 7, 2017Assignee: Rambus Inc.Inventors: Haw-Jyh Liaw, Xingchao Yuan, Mark A. Horowitz
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Publication number: 20140070819Abstract: A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.Type: ApplicationFiled: June 18, 2013Publication date: March 13, 2014Inventors: Haw-Jyh Liaw, Xingchao Yuan, Mark A. Horowitz
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Patent number: 8599983Abstract: A clock and data recovery circuit may comprise a first transmission line comprising a plurality of segments of a first predetermined length. The first transmission line receives and propagates a clock signal through the segments of the first predetermined length. The clock and data recovery circuit may further comprise a second transmission line comprising a plurality of segments of a second predetermined length. The second transmission line receives data from a serial bit stream and propagates the data through the segments of the second predetermined length. In some embodiments, the first or second transmission line further comprise taps to extract, from the segments of the second predetermined length, a plurality of delayed data signals. The clock and data recovery circuit may further comprise a plurality of sampling circuits, coupled to the first and second transmission lines, to generate samples from the delayed data signals and the delayed clock signals.Type: GrantFiled: January 17, 2012Date of Patent: December 3, 2013Assignee: NetLogic Microsystems, Inc.Inventors: Stefanos Sidiropoulos, Haw-Jyh Liaw
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Patent number: 8489345Abstract: A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.Type: GrantFiled: September 26, 2011Date of Patent: July 16, 2013Assignee: Rambus Inc.Inventors: Haw-Jyh Liaw, Xiangchao Yuan, Mark A. Horowitz
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Patent number: 8364878Abstract: A memory module includes a substrate, a plurality of signal lines, a clock line and a plurality of memory devices. The plurality of signal lines including first and second signal lines routed alongside one another where, for each of the first and second signal lines, a respective signal, starting at a corresponding first edge finger, traverses in sequence, a respective first segment of a respective signal line, a respective turn portion of the respective signal line, and a respective second segment of the respective signal line. The clock line is to provide a clock signal that traverses in sequence, a second edge finger, the first segment of the clock line, the turn portion of the clock line, and the second segment of the clock line. The respective signals traverse and the clock signal line arrive at the plurality of memory devices in sequence.Type: GrantFiled: February 3, 2012Date of Patent: January 29, 2013Assignee: Rambus Inc.Inventors: Haw-Jyh Liaw, David Nguyen
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Publication number: 20120230450Abstract: A clock and data recovery circuit may comprise a first transmission line comprising a plurality of segments of a first predetermined length. The first transmission line receives and propagates a clock signal through the segments of the first predetermined length. The clock and data recovery circuit may further comprise a second transmission line comprising a plurality of segments of a second predetermined length. The second transmission line receives data from a serial bit stream and propagates the data through the segments of the second predetermined length. In some embodiments, the first or second transmission line further comprise taps to extract, from the segments of the second predetermined length, a plurality of delayed data signals. The clock and data recovery circuit may further comprise a plurality of sampling circuits, coupled to the first and second transmission lines, to generate samples from the delayed data signals and the delayed clock signals.Type: ApplicationFiled: January 17, 2012Publication date: September 13, 2012Inventors: Stefanos Sidiropoulos, Haw-Jyh Liaw
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Patent number: 8214575Abstract: A memory module includes a first signal line to carry a first signal. The first signal line has (i) a first line segment disposed along a length of the memory module and coupled to a termination, and (ii) a second line segment disposed along a width of the memory module and coupled to an edge finger. The first line segment and the second line segment are coupled together at a turn. A first synchronous memory device and a second synchronous memory device are coupled to the first line segment. The first signal arrives at the first synchronous memory device and the second synchronous memory device in a sequential manner. The memory module includes a clock line routed alongside the first signal line. A clock signal arrives at the first synchronous memory device and the second synchronous memory device in sequence alongside the first signal traversing along the first signal line.Type: GrantFiled: December 21, 2010Date of Patent: July 3, 2012Assignee: Rambus Inc.Inventors: Haw-Jyh Liaw, David Nguyen
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Publication number: 20120144085Abstract: A memory module includes a substrate, a plurality of signal lines, a clock line and a plurality of memory devices. The plurality of signal lines including first and second signal lines routed alongside one another where, for each of the first and second signal lines, a respective signal, starting at a corresponding first edge finger, traverses in sequence, a respective first segment of a respective signal line, a respective turn portion of the respective signal line, and a respective second segment of the respective signal line. The clock line is to provide a clock signal that traverses in sequence, a second edge finger, the first segment of the clock line, the turn portion of the clock line, and the second segment of the clock line. The respective signals traverse and the clock signal line arrive at the plurality of memory devices in sequence.Type: ApplicationFiled: February 3, 2012Publication date: June 7, 2012Inventors: Haw-Jyh Liaw, David Nguyen
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Patent number: 8155236Abstract: A data receiver circuit includes a transmission line to generate the appropriate timing for clock and data recovery. The transmission line receives a reference signal, and propagates the reference signal through at least two segments of predetermined lengths. The transmission line is configured with a first tab to extract, from the first predetermined length, a first delayed signal, and a second tab to extract, from the second predetermined length, a second delayed signal. A sampling circuit generates samples, at a first time period, from an input signal and the first delayed signal. The sampling circuit also generates samples, at a second time period, from the input signal and the second delayed signal. A capacitance control device to adjust the capacitance of the transmission line is disclosed.Type: GrantFiled: June 21, 2002Date of Patent: April 10, 2012Assignee: NetLogic Microsystems, Inc.Inventors: Stefanos Sidiropoulos, Haw-Jyh Liaw
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Publication number: 20120072153Abstract: A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.Type: ApplicationFiled: September 26, 2011Publication date: March 22, 2012Applicant: Rambus Inc.Inventors: Haw-Jyh LIAW, Xingchao Yuan, Mark A. Horowitz
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Patent number: 8102936Abstract: A data receiver circuit includes a transmission line to generate the appropriate timing for clock and data recovery. The transmission line receives a reference signal, and propagates the reference signal through at least two segments of predetermined lengths. The transmission line is configured with a first tab to extract, from the first predetermined length, a first delayed signal, and a second tab to extract, from the second predetermined length, a second delayed signal. A sampling circuit generates samples, at a first time period, from an input signal and the first delayed signal. The sampling circuit also generates samples, at a second time period, from the input signal and the second delayed signal. A capacitance control device to adjust the capacitance of the transmission line is disclosed.Type: GrantFiled: October 31, 2007Date of Patent: January 24, 2012Assignee: NetLogic Microsystems, Inc.Inventors: Stefanos Sidiropoulos, Haw-Jyh Liaw
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Patent number: 8055458Abstract: A technique for determining performance characteristics of electronic devices and systems is disclosed. In one embodiment, the technique is realized by measuring a first response on a first transmission line from a single pulse transmitted on the first transmission line, and then measuring a second response on the first transmission line from a single pulse transmitted on at least one second transmission line, wherein the at least one second transmission line is substantially adjacent to the first transmission line. The worst case bit sequences for transmission on the first transmission line and the at least one second transmission line are then determined based upon the first response and the second response for determining performance characteristics associated with the first transmission line.Type: GrantFiled: May 22, 2009Date of Patent: November 8, 2011Assignee: Rambus Inc.Inventors: Haw-Jyh Liaw, Xiangchao Yuan, Mark A. Horowitz
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Publication number: 20110090727Abstract: A memory module includes a first signal line to carry a first signal. The first signal line has (i) a first line segment disposed along a length of the memory module and coupled to a termination, and (ii) a second line segment disposed along a width of the memory module and coupled to an edge finger. The first line segment and the second line segment are coupled together at a turn. A first synchronous memory device and a second synchronous memory device are coupled to the first line segment. The first signal arrives at the first synchronous memory device and the second synchronous memory device in a sequential manner. The memory module includes a clock line routed alongside the first signal line. A clock signal arrives at the first synchronous memory device and the second synchronous memory device in sequence alongside the first signal traversing along the first signal line.Type: ApplicationFiled: December 21, 2010Publication date: April 21, 2011Inventors: Haw-Jyh Liaw, David Nguyen
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Patent number: 7870322Abstract: A memory module includes a first signal line to carry a first signal. The first signal line has (i) a first line segment disposed along a length of the memory module and coupled to a termination, and (ii) a second line segment disposed along a width of the memory module and coupled to an edge finger. The first line segment and the second line segment are coupled together at a turn. A first synchronous memory device and a second synchronous memory device are coupled to the first line segment. The first signal arrives at the first synchronous memory device and the second synchronous memory device in a sequential manner. The memory module includes a clock line routed alongside the first signal line. A clock signal arrives at the first synchronous memory device and the second synchronous memory device in sequence alongside the first signal traversing along the first signal line.Type: GrantFiled: April 17, 2009Date of Patent: January 11, 2011Assignee: Rambus Inc.Inventors: Haw-Jyh Liaw, David Nguyen
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Patent number: 7856570Abstract: A method and system for shaping an electronic pulse with a two-pulse response. An input node receives an initial electronic pulse and splits the electronic pulse into a first path and a second path. An output node combines together the first path and the second path into an output path, and transmits a shaped electronic pulse, matched to an output impedance. An Ethernet chip generates two pulses and transmits the pulses along a first path and a second path respectively. A power combiner/splitter combines together the pulses along the first path and the second path into an output path, and transmits a shaped electronic pulse, matched to an output impedance.Type: GrantFiled: August 24, 2007Date of Patent: December 21, 2010Assignee: NetLogic Microsystems, Inc.Inventors: Haw-Jyh Liaw, Shwetabh Verma
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Publication number: 20100188128Abstract: An initial pulse signal is split into a first pulse signal and a second pulse signal. The first pulse signal is delayed through a first impedance to generate a first delayed pulse signal. The first impedance attenuates the first delayed pulse signal to generate an attenuated pulse signal. The second pulse signal is delayed through a second impedance to generate a second delayed pulse signal. The first delayed pulse signal and the attenuated pulse signal are combined to generate the two-pulse response signal.Type: ApplicationFiled: March 19, 2010Publication date: July 29, 2010Inventors: Haw-Jyh Liaw, Shwetabh Yerma