Abstract: According to one embodiment, a computing device includes an element section, a first conductive portion, a second conductive portion, a first coupling conductive portion, and a controller. The element section includes a first structure, a second structure, and a first coupling structure. The first structure includes a first cavity resonator having a first resonance frequency, a first other cavity resonator having a first other resonance frequency, and a first coupler configured to couple the first cavity resonator and the first other cavity resonator. The first other resonance frequency is lower than the first resonance frequency. The second structure includes a second cavity resonator having a second resonance frequency, a second other cavity resonator having a second other resonance frequency, and a second coupler configured to couple the second cavity resonator and the second other cavity resonator. The second other resonance frequency is lower than the second resonance frequency.

Abstract: According to one embodiment, a computing device includes an element section, a first control member, and a controller. The element section includes a first qubit including a first loop including a plurality of first Josephson junctions, and a second qubit including a second loop including a plurality of second Josephson junctions. The second qubit is configured to be connected with the first qubit. The controller is configured to cause the first control member to execute a first operation. In the first operation, the controller is configured to cause the first control member to apply a pulse wave including a DC component to the first loop while applying a first signal wave including a first AC component to the first loop.

Abstract: According to one embodiment, a calculating device includes a first memory, a second memory, a third memory, a first arithmetic module, a second arithmetic module, a first conductive line electrically connecting a first output terminal of the first memory and a first input terminal of the first arithmetic module, a second conductive line electrically connecting a second output terminal of the first memory and a first input terminal of the second arithmetic module, a third conductive line electrically connecting a first output terminal of the second memory and a second input terminal of the second arithmetic module, a fourth conductive line electrically connecting a first output terminal of the third memory and a third input terminal of the second arithmetic module, and a fifth conductive line electrically connecting a first output terminal of the second arithmetic module and a second input terminal of the first arithmetic module.

Abstract: According to one embodiment, a calculating device includes an acquisition part configured to acquire a problem parameter set, and a processor. The processor is configured to repeatedly perform a first variable update of updating a first variable set, and a second variable update of updating a second variable set. In the second variable update, the processor updates the second variable set by using a function including a first term and a second term. The first term includes the first variable set and a bifurcation parameter set. The second term includes the first variable set and the problem parameter set acquired by the acquisition part. In the first variable update, the processor updates the first variable set by using the second variable set updated in the second variable update. The bifurcation parameter set includes a first bifurcation parameter and a second bifurcation parameter.

Abstract: An electronic circuit includes a band-pass filter, and at least one first circuit. The band-pass filter includes a plurality of filter resonators. Two adjacent filter resonators included in the filter resonators are mutually couplable. The first circuit includes a first qubit and a first readout resonator. The first readout resonator is couplable with the first qubit and one of the filter resonators. A passband of the band-pass filter includes a first passband and a second passband. A magnitude of a first ripple of the first passband is not more than 1/10 of a magnitude of a second ripple of the second passband.

Abstract: According to one embodiment, a computing device includes an element section. The element section includes a first structure and a second structure. The first structure includes a first base and a first qubit fixed to the first base. The second structure includes a second base, a second qubit fixed to the second base, and a first tunable coupler fixed to the second base. The first tunable coupler includes a first portion and a second portion. The first portion is capacitively coupled with the first qubit, and the second portion is capacitively coupled with the second qubit.

Abstract: According to one embodiment, a calculating device includes a first memory, a second memory, a third memory, a first arithmetic module, a second arithmetic module, a first conductive line electrically connecting a first output terminal of the first memory and a first input terminal of the first arithmetic module, a second conductive line electrically connecting a second output terminal of the first memory and a first input terminal of the second arithmetic module, a third conductive line electrically connecting a first output terminal of the second memory and a second input terminal of the second arithmetic module, a fourth conductive line electrically connecting a first output terminal of the third memory and a third input terminal of the second arithmetic module, and a fifth conductive line electrically connecting a first output terminal of the second arithmetic module and a second input terminal of the first arithmetic module.

Abstract: According to one embodiment, an information processing device includes an acquisition part and a processor. The acquisition part is configured to acquire input information related to a plurality of target devices. The processor is configured to perform first processing and second processing. In the first processing, the processor derives a first solution of a problem determined according to the input information. In the second processing, the processor derives output information by using the 10 first solution, and a plurality of scores calculated from the first solution and second information.

Abstract: According to one embodiment, an electronic circuit includes a first base and a first structure. The first base includes a first face, a first side face, a second side face, a third side face, and a third other side face. The first side face, the second side face, the third side face, and the third other side face cross a plane along the first face. The first structure includes a first nonlinear element, and first to third conductive members. The first nonlinear element includes first and second element portions, and an intermediate Josephson junction provided between the first element portion and the second element portion. The first conductive member includes a first region and a first connection region. The second conductive member includes a second region and a second connection region. The third conductive member includes a third region and a third other region.

Abstract: According to one embodiment, a coupler includes first to fourth capacitors, first and second inductors, and a first Josephson junction. The first capacitor includes a first capacitor end portion and a first capacitor other-end portion. The first inductor includes a first inductor end portion, and a first inductor other-end portion. The second inductor includes a second inductor end portion, and a second inductor other-end portion. The first Josephson junction includes a first Josephson junction end portion, and a first Josephson junction other-end portion. A space is surrounded with the first inductor, the second inductor, and the first Josephson junction. The third capacitor includes a third capacitor end portion, and a third capacitor other-end portion. The fourth capacitor includes a fourth capacitor end portion, and a fourth capacitor other-end portion.

Abstract: According to one embodiment, an electronic circuit includes an element section. The element section includes a first coupler, a first resonator, and a first conductive member. The first coupler is configured to be capacitively coupled with a first qubit and a second qubit. The first coupler includes a loop. The first resonator is configured to be inductively coupled with the loop. The first conductive member is configured to be capacitively coupled with the first resonator. An excitation signal for exciting the first resonator is inputted to the first conductive member.

Abstract: A calculation apparatus according to an embodiment includes matrix multiplication circuitry, time evolution circuitry, management circuitry, and output circuitry. The matrix multiplication circuitry calculates N second intermediate variables at a first time point by matrix multiplication between N (N>=2) first intermediate variables at the first time point and a preset coefficient matrix in N rows and N columns. The time evolution circuitry calculates N first variables at a second time point and N first intermediate variables at the second time point, the second time point being a time point following one sampling period after the first time point. The management circuitry increments time point from a start time point for each sampling period and controls the above circuitry to perform a process for each time point. The output circuitry outputs N first variables at a preset end time point.

Abstract: A search device updates positions and momentums of a plurality of virtual particles, for each unit time from an initial time to an end time. The search device, for each unit time, calculates, for each of the particles, a position at a target time of a corresponding particle, calculates, for each of a plurality of nodes, a first accumulative value by cumulatively adding positions at the target time of two or more particles corresponding to outgoing two or more directed edges, calculates, for each of the nodes, a second accumulative value by cumulatively adding positions at the target time of two or more particles corresponding to incoming two or more directed edges, and calculates, for each of the particles, a momentum at the target time of a corresponding particle based on the first accumulative value and the second accumulative value.

Abstract: According to one embodiment, a coupler includes first to fourth capacitors, first and second inductors, and a first Josephson junction. The first capacitor includes a first capacitor end portion and a first capacitor other-end portion. The first inductor includes a first inductor end portion, and a first inductor other-end portion. The second inductor includes a second inductor end portion, and a second inductor other-end portion. The first Josephson junction includes a first Josephson junction end portion, and a first Josephson junction other-end portion. A space is surrounded with the first inductor, the second inductor, and the first Josephson junction. The third capacitor includes a third capacitor end portion, and a third capacitor other-end portion. The fourth capacitor includes a fourth capacitor end portion, and a fourth capacitor other-end portion.

Abstract: According to one embodiment, an encoder includes a first element part and a controller. The first element part includes a first qubit, a second qubit couplable with the first qubit, a third qubit couplable with the second qubit, a fourth qubit couplable with the third qubit, a fifth qubit couplable with the fourth qubit, a sixth qubit couplable with the fifth qubit, a seventh qubit couplable with the sixth qubit, an eighth qubit couplable with the seventh qubit, and a ninth qubit couplable with the eighth qubit. The controller is configured to perform a first control. The first control includes encoding a surface code having a code distance of 3.

Abstract: According to one embodiment, a calculating device includes a processor repeating a processing procedure. The processing procedure includes a first variable update and a second variable update. The first variable update includes updating an ith entry of a first variable xi by adding a first function to the ith entry of the first variable xi before the first variable update. The second variable update includes updating the ith entry of the second variable yi by adding a second function and a third function to the ith entry of the second variable yi before the second variable update. The processor performs at least an output of at least one of the ith entry of the first variable xi obtained after the repeating of the processing procedure or a function of the ith entry of the first variable xi obtained after the repeating of the processing procedure.

Abstract: According to an embodiment, a calculation device includes a memory and one or more processors configured to update, for elements each associated with first and second variables, the first and second variables for each unit time, sequentially for the unit times and alternately between the first and second variables. In a calculation process for each unit time, the one or more processors are configured to: for each of the elements, update the first variable based on the second variable; update the second variable based on the first variables of the elements; when the first variable is smaller than a first value, change the first variable to a value of the first value or more and a threshold value or less; and when the first variable is greater than a second value, change the first variable to a value of the threshold value or more and the second value or less.

Abstract: According to one embodiment, a calculating device includes a processor repeating a processing procedure. The processing procedure includes a first variable update and a second variable update. The first variable update includes updating an ith entry of a first variable xi by adding a first function to the ith entry of the first variable xi before the first variable update. The second variable update includes updating the ith entry of the second variable yi by adding a second function and a third function to the ith entry of the second variable yi before the second variable update. The processor performs at least an output of at least one of the ith entry of the first variable xi obtained after the repeating of the processing procedure or a function of the ith entry of the first variable xi obtained after the repeating of the processing procedure.

Abstract: According to one embodiment, a communication system includes a base station based on a communication standard and an allocation information generation device from the base station. The allocation information generation device comprises first and second generators. The first and the second generators output first and second allocation information until a first time elapses after an allocation request is received. The allocation information generation device transmits, to the base station, one of the first and the second allocation information which satisfies a constraint defined by the communication standard.

Abstract: According to an embodiment, an information processing system solves a combinatorial optimization problem. The information processing system includes an Ising machine and a host unit. The Ising machine is hardware configured to perform a search process for searching for the ground state of an Ising model that represents the combinatorial optimization problem. The host unit is hardware connected to the Ising machine via an interface and configured to control the Ising machine. In the search process, for each of a plurality of Ising spins, the Ising machine alternately repeats an auxiliary variable update process for updating an auxiliary variable by a main variable and a main variable update process for updating the main variable by the auxiliary variable multiple times. Prior to the search process, the host unit transmits, to the Ising machine, an initial value of the auxiliary variable corresponding to each of the plurality of Ising spins.