Patents by Inventor Hayato Nakano

Hayato Nakano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11069621
    Abstract: Provided is a semiconductor device including an input terminal including a P terminal and an N terminal; a laminated circuit substrate connected to the input terminal; a power substrate provided above the laminated circuit substrate; a connecting section electrically connecting the laminated circuit substrate and the power substrate; a capacitor provided in a conduction path between the P terminal and the N terminal; and a resistor provided in series with the capacitor in the conduction path between the P terminal and the N terminal. The capacitor may be provided in a region where the input terminal or the connecting section is provided, in an overhead view.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: July 20, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hayato Nakano
  • Publication number: 20210143147
    Abstract: A semiconductor module includes: a first metal plate including a first mount part joined with a bottom-surface electrode of a first switching element, a second mount part joined with a positive-electrode terminal, and a first narrow part between the first and second mount parts and being narrower than a part jointing the first switching element to the first mount part and the positive-electrode terminal; a second metal plate being joined with a bottom-surface electrode of a second switching element, and connected to a top-surface electrode of the first switching element; a third metal plate including a sixth mount part joined with a negative-electrode terminal, a seventh mount part connected to a top-surface electrode of the second switching element, and being narrower than the negative-electrode terminal, and a second narrow part between the sixth and seventh mount parts; and a snubber circuit connecting the first and second narrow parts.
    Type: Application
    Filed: September 28, 2020
    Publication date: May 13, 2021
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventor: Hayato NAKANO
  • Patent number: 10966322
    Abstract: A semiconductor device includes: a sealed unit that seals a semiconductor element therein; a connection terminal that is electrically connected to the semiconductor element and is provided so as to project outward from the sealed unit; and a pedestal that is provided to surround a bottom part of an exposed portion of the connection terminal that is exposed from the sealed unit. The pedestal has a base attached to the sealed unit and a guide part that has an inclined side face.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: March 30, 2021
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hayato Nakano
  • Publication number: 20200388937
    Abstract: External connection reliability is improved with an external connector including an external connection terminal, and a nut provided on a bottom surface side of the external connection terminal. The external connection terminal has a conductor, a first metal layer provided on an upper surface of the conductor, a second metal layer provided on the first metal layer, and a bottom surface metal layer provided on a bottom surface of the conductor.
    Type: Application
    Filed: February 19, 2020
    Publication date: December 10, 2020
    Inventors: Hayato NAKANO, Shun SAKAI
  • Patent number: 10784214
    Abstract: A semiconductor module includes: a first lead frame connected to a plurality of semiconductor chips in a first arm circuit; a second lead frame connected to a plurality of semiconductor chips in a second arm circuit; a first main terminal connected to the first lead frame; and a second main terminal connected to the second lead frame, wherein each of the first lead frame and second lead frame has a facing part, a first terminal connection portion connected to the first main terminal is provided at a first end portion of the first lead frame, a second terminal connection portion connected to the second main terminal is provided at a second end portion of the second lead frame, and the first terminal connection portion and second terminal connection portion are arranged on opposite sides when viewed from the facing parts of the first lead frame and second lead frame.
    Type: Grant
    Filed: January 29, 2019
    Date of Patent: September 22, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Shin Soyano, Hayato Nakano, Keiichi Higuchi, Akihiro Osawa
  • Publication number: 20200258834
    Abstract: An external connection terminal of a semiconductor module is provided. The external connection terminal includes a conductor having an upper surface and a lower surface; a plated layer configured to cover the upper surface of the conductor; and a nut provided on the lower surface-side of the conductor for receiving a screw penetrating the conductor. The plated layer includes a low contact resistance region overlapping a region in which the nut is provided, and a high contact resistance region that is a region except the low contact resistance region, as seen from above, and the plated layer includes a convex portion and a concave portion on a surface in the high contact resistance region.
    Type: Application
    Filed: January 7, 2020
    Publication date: August 13, 2020
    Inventor: Hayato NAKANO
  • Patent number: 10741550
    Abstract: A reverse-conducting semiconductor device includes a semiconductor chip having a top surface, a first side and a second side orthogonal to the first side in a plan view, in which a plurality of transistor regions and a plurality of diode regions are alternately arranged and an upper-electrode is provided on top surface-sides of the transistor regions and the diode regions; and a wiring member having a flat-plate portion having a rectangular-shape which is metallurgically jointed to the upper-electrode via a joint member above the diode regions. The wiring member has a conductive wall rising from a bending edge of the flat-plate portion in a direction opposite to the upper-electrode, and the bending edge of the flat-plate portion is arranged parallel to the first side.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: August 11, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hayato Nakano, Keiichi Higuchi, Akihiro Osawa
  • Publication number: 20200006237
    Abstract: Provided is a semiconductor device including an input terminal including a P terminal and an N terminal; a laminated circuit substrate connected to the input terminal; a power substrate provided above the laminated circuit substrate; a connecting section electrically connecting the laminated circuit substrate and the power substrate; a capacitor provided in a conduction path between the P terminal and the N terminal; and a resistor provided in series with the capacitor in the conduction path between the P terminal and the N terminal. The capacitor may be provided in a region where the input terminal or the connecting section is provided, in an overhead view.
    Type: Application
    Filed: June 3, 2019
    Publication date: January 2, 2020
    Inventor: Hayato NAKANO
  • Publication number: 20190355718
    Abstract: A reverse-conducting semiconductor device includes a semiconductor chip having a top surface, a first side and a second side orthogonal to the first side in a plan view, in which a plurality of transistor regions and a plurality of diode regions are alternately arranged and an upper-electrode is provided on top surface-sides of the transistor regions and the diode regions; and a wiring member having a flat-plate portion having a rectangular-shape which is metallurgically jointed to the upper-electrode via a joint member above the diode regions. The wiring member has a conductive wall rising from a bending edge of the flat-plate portion in a direction opposite to the upper-electrode, and the bending edge of the flat-plate portion is arranged parallel to the first side.
    Type: Application
    Filed: March 22, 2019
    Publication date: November 21, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Hayato Nakano, Keiichi Higuchi, Akihiro Osawa
  • Publication number: 20190254167
    Abstract: A semiconductor device includes: a sealed unit that seals a semiconductor element therein; a connection terminal that is electrically connected to the semiconductor element and is provided so as to project outward from the sealed unit; and a pedestal that is provided to surround a bottom part of an exposed portion of the connection terminal that is exposed from the sealed unit. The pedestal has a base attached to the sealed unit and a guide part that has an inclined side face.
    Type: Application
    Filed: January 7, 2019
    Publication date: August 15, 2019
    Applicant: Fuji Electric Co., Ltd.
    Inventor: Hayato NAKANO
  • Publication number: 20190157221
    Abstract: A semiconductor module includes: a first lead frame connected to a plurality of semiconductor chips in a first arm circuit; a second lead frame connected to a plurality of semiconductor chips in a second arm circuit; a first main terminal connected to the first lead frame; and a second main terminal connected to the second lead frame, wherein each of the first lead frame and second lead frame has a facing part, a first terminal connection portion connected to the first main terminal is provided at a first end portion of the first lead frame, a second terminal connection portion connected to the second main terminal is provided at a second end portion of the second lead frame, and the first terminal connection portion and second terminal connection portion are arranged on opposite sides when viewed from the facing parts of the first lead frame and second lead frame.
    Type: Application
    Filed: January 29, 2019
    Publication date: May 23, 2019
    Inventors: Shin SOYANO, Hayato NAKANO, Keiichi HIGUCHI, Akihiro OSAWA
  • Patent number: 10170395
    Abstract: A semiconductor device including a semiconductor module 10A, a semiconductor module 10B that has a lower switching voltage threshold than the semiconductor module 10A, and busbars 331 and 32 that connect the semiconductor module 10A and the semiconductor module 10B in parallel to a common terminal. The semiconductor module 10B is connected at a connection point on the busbar 32 at which the inductance relative to the common terminal is higher than that of the semiconductor module 10A. The semiconductor module 10B with the low threshold voltage is turned ON faster than the semiconductor module 10A with the high threshold voltage for input of a common switching voltage, but can restrict the rising of the current due to the high inductance of the busbar 32, thereby enabling restriction of the current imbalance.
    Type: Grant
    Filed: January 27, 2017
    Date of Patent: January 1, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hayato Nakano, Hideyo Nakamura
  • Patent number: 10163868
    Abstract: A semiconductor device includes an insulating substrate having an insulating plate and a circuit plate; a semiconductor chip having a front surface provided with a gate electrode and a source electrode, and a rear surface fixed to the circuit plate; a printed circuit board facing the insulating substrate, and including a first metal layer and a second metal layer; a first conductive post having two ends electrically and mechanically connected to the gate electrode and the first metal layer; a second conductive post having two ends electrically and mechanically connected to the source electrode and the second metal layer; and a circuit impedance reducing element electrically connected between the gate electrode and the source electrode through the first conductive post and the second conductive post.
    Type: Grant
    Filed: October 7, 2015
    Date of Patent: December 25, 2018
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Masafumi Horio, Yoshinari Ikeda, Hideyo Nakamura, Hayato Nakano
  • Publication number: 20180174987
    Abstract: A semiconductor device is provided that includes a semiconductor chip having a main terminal and a control terminal, a main connection pin electrically connected to the main terminal, and a control connection pin electrically connected to the control terminal and having an electrical resistance higher than that of the main connection pin. The control connection pin may be a control internal connection pin or a control external connection pin. The control connection pin may include material having an electrical resistivity higher than that of material of the main connection pin. The control connection pin may have a shape different from that of the main connection pin.
    Type: Application
    Filed: October 26, 2017
    Publication date: June 21, 2018
    Inventors: Mikiya CHOUNABAYASHI, Ryohei MAKINO, Hayato NAKANO
  • Patent number: 9818852
    Abstract: In some aspects of the invention, an n-type field-stop layer can have a total impurity of such an extent that a depletion layer spreading in response to an application of a rated voltage stops inside the n-type field-stop layer together with the total impurity of an n? type drift layer. Also, the n-type field-stop layer can have a concentration gradient such that the impurity concentration of the n-type field-stop layer decreases from a p+ type collector layer toward a p-type base layer, and the diffusion depth is 20 ?m or more. Furthermore, an n+ type buffer layer of which the peak impurity concentration can be higher than that of the n-type field-stop layer at 6×1015 cm?3 or more, and one-tenth or less of the peak impurity concentration of the p+ type collector layer, can be included between the n-type field-stop layer and p+ type collector layer.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: November 14, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takashi Yoshimura, Hidenao Kuribayashi, Yuichi Onozawa, Hayato Nakano, Daisuke Ozaki
  • Patent number: 9812561
    Abstract: In some aspects of the invention, an n-type field-stop layer can have a total impurity of such an extent that a depletion layer spreading in response to an application of a rated voltage stops inside the n-type field-stop layer together with the total impurity of an n? type drift layer. Also, the n-type field-stop layer can have a concentration gradient such that the impurity concentration of the n-type field-stop layer decreases from a p+ type collector layer toward a p-type base layer, and the diffusion depth is 20 ?m or more. Furthermore, an n+ type buffer layer of which the peak impurity concentration can be higher than that of the n-type field-stop layer at 6×1015 cm?3 or more, and one-tenth or less of the peak impurity concentration of the p+ type collector layer, can be included between the n-type field-stop layer and p+ type collector layer.
    Type: Grant
    Filed: March 15, 2016
    Date of Patent: November 7, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takashi Yoshimura, Hidenao Kuribayashi, Yuichi Onozawa, Hayato Nakano, Daisuke Ozaki
  • Patent number: 9773936
    Abstract: A semiconductor device is provided, which has a wide-bandgap semiconductor element, such as a SiC element, and which includes a sensor capable of responding sufficiently to characteristic requirements for protecting and controlling the semiconductor element. The semiconductor device includes a wide-bandgap semiconductor element mounted on a substrate; and a light-receiving element that receives light emitted from the wide-bandgap semiconductor element when the wide-bandgap semiconductor element is in a conduction state.
    Type: Grant
    Filed: November 16, 2015
    Date of Patent: September 26, 2017
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventor: Hayato Nakano
  • Publication number: 20170263535
    Abstract: A semiconductor device including a semiconductor module 10A, a semiconductor module 10B that has a lower switching voltage threshold than the semiconductor module 10A, and busbars 331 and 32 that connect the semiconductor module 10A and the semiconductor module 10B in parallel to a common terminal. The semiconductor module 10B is connected at a connection point on the busbar 32 at which the inductance relative to the common terminal is higher than that of the semiconductor module 10A. The semiconductor module 10B with the low threshold voltage is turned ON faster than the semiconductor module 10A with the high threshold voltage for input of a common switching voltage, but can restrict the rising of the current due to the high inductance of the busbar 32, thereby enabling restriction of the current imbalance.
    Type: Application
    Filed: January 27, 2017
    Publication date: September 14, 2017
    Inventors: Hayato NAKANO, Hideyo NAKAMURA
  • Publication number: 20170077068
    Abstract: A semiconductor device includes an insulating substrate having an insulating plate and a circuit plate; a semiconductor chip having a front surface provided with a gate electrode and a source electrode, and a rear surface fixed to the circuit plate; a printed circuit board facing the insulating substrate, and including a first metal layer and a second metal layer; a first conductive post having two ends electrically and mechanically connected to the gate electrode and the first metal layer; a second conductive post having two ends electrically and mechanically connected to the source electrode and the second metal layer; and a circuit impedance reducing element electrically connected between the gate electrode and the source electrode through the first conductive post and the second conductive post.
    Type: Application
    Filed: October 7, 2015
    Publication date: March 16, 2017
    Inventors: Masafumi HORIO, Yoshinari IKEDA, Hideyo NAKAMURA, Hayato NAKANO
  • Publication number: 20170077924
    Abstract: The semiconductor device includes a switching arm unit in which first and second wide bandgap semiconductor elements, each having a body diode, are connected in series between a positive line and a negative line; a current detecting unit that detects a current in at least a wide bandgap semiconductor element in which a flyback current flows; and a semiconductor element driving unit that drives the first and second wide bandgap semiconductor elements. When driving one of the wide bandgap semiconductor elements, the semiconductor element driving unit determines, by referring to a fault inhibiting characteristic curve, whether a flyback current detection value of the other wide bandgap semiconductor elements falls within a fault growth region or a fault inhibiting region, and when a result of the determination indicates that the flyback current detection value is within the fault growth region, inhibits a current flowing in the one wide bandgap semiconductor element.
    Type: Application
    Filed: August 9, 2016
    Publication date: March 16, 2017
    Applicant: Fuji Electric Co., Ltd.
    Inventors: Hayato NAKANO, Ryohei TAKAYANAGI