Abstract: A video decoding apparatus for decoding encoded video data to continuously produce decoded pictures. The video data includes a series of pictures, each picture contains a series of slices, and each slice contains a series of macroblocks. A dequantizer performs dequantization of the video data based upon a quantization threshold value. A motion-vector restoring circuit restores data for each macroblock. A direct current error detector is provided to detect erroneous macroblocks based upon the dequantized data. A motion-area error detector is provided to detect erroneous macroblocks based upon the restored motion vector data. An erroneous macroblock is replaced by a corresponding macroblock from a preceding picture. Subsequent macroblocks in a slice may also be replaced by corresponding macroblocks from a preceding picture.

Abstract: An MPEG video decoder capable of preventing a buffer for storing a video stream from overflowing and/or underflowing. The video decoding apparatus decodes a coded video bit stream including a series of pictures to produce decoded pictures. The video decoding apparatus includes: a bit buffer for temporarily storing the video bit stream, a decoding circuit for receiving the video bit stream output from the bit buffer and decoding the video bit stream to produce decoded pictures, and a video bit stream control circuit for controlling an amount of the video bit stream to be supplied to the decoding circuit from the bit buffer based on an amount of data of the video bit stream stored in the bit buffer.

Abstract: Discrete cosine transform circuits suitable for inverse discrete cosine transform (IDCT) or forward discrete cosine transform (FDCT) are disclosed. An IDCT circuit includes a group of multipliers and a group of adders/subtracters. The multipliers receive plural pieces of input data which are externally supplied in parallel. Each multiplier has a cosine constant to multiply to the received input data. The adders/subtracters receive multiplication results from the multipliers and perform addition/subtraction thereon to produce output data, which is the result of inverse discrete cosine transform of the input data. An FDCT circuit includes a group of input-stage adders/subtracters, a group of multipliers, and a group of output-stage adders. The input-stage adders/subtracters perform addition/subtraction on input data which are externally supplied in parallel. Computation results of the input-stage adders/subtracters is supplied to the multipliers.