Patents by Inventor Hazuki Okabayashi
Hazuki Okabayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9170841Abstract: A multiprocessor system includes a plurality of processors, each including a task scheduler that determines a task execution order of tasks in a task set to be executed by the processors within a task period which is defined as a period in repeated execution of the task sets; and a scheduler management device having a command unit configured to issue a command for at least one of the task schedulers to change the task execution order, wherein each of the at least one of the task schedulers, when receiving the command from the command unit, changes the task execution order of the corresponding processor.Type: GrantFiled: December 18, 2012Date of Patent: October 27, 2015Assignee: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.Inventors: Kiyokazu Fukuzaki, Masanori Henmi, Hazuki Okabayashi, Hiroyuki Murata, Takatsugu Sawai, Hiroyuki Shigeta
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Publication number: 20110179227Abstract: A cache memory and method for controlling the cache memory. The cache memory selects, from an access address, a unique set from among a plurality of sets, each access set including a plurality of cache entries. Each cache entry holds unit data for caching. The cache memory holds, for each of the cache entries, order data that indicates an access order of the cache entries in each set, and replaces a cache entry that is oldest in the access order. The cache memory modifies the order data regardless of an actual access order, and selects, based on the modified order data, a cache entry to be replaced.Type: ApplicationFiled: March 30, 2011Publication date: July 21, 2011Applicant: PANASONIC CORPORATIONInventors: Hazuki OKABAYASHI, Ryuta NAKANISHI, Tetsuya TANAKA, Shuji MIYASAKA
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Patent number: 7970998Abstract: A cache memory of the present invention includes a second cache memory that is operated in parallel with a first cache memory, a judgment unit which, when a cache miss occurs in both of the first cache memory and the second cache memory, makes a true or false judgment relating to an attribute of data for which memory access resulted in the cache miss, and a controlling unit which stores memory data in the second cache memory when a judgment of true is made, and stores the memory data in the first cache memory when a judgment of false is made.Type: GrantFiled: March 17, 2006Date of Patent: June 28, 2011Assignee: Panasonic CorporationInventors: Takao Yamamoto, Tetsuya Tanaka, Ryuta Nakanishi, Masaitsu Nakajima, Keisuke Kaneko, Hazuki Okabayashi
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Patent number: 7953935Abstract: A cache memory system which readily accepts software control for processing includes: a cache memory provided between a processor and memory; and a TAC (Transfer and Attribute Controller) for controlling the cache memory. The TAC receives a command which indicates a transfer and an attribute operation of cache data and a target for the operation, resulting from the execution of a predetermined instruction by the processor, so as to request the operation indicated by the command against the address to the cache memory.Type: GrantFiled: February 8, 2006Date of Patent: May 31, 2011Assignee: Panasonic CorporationInventors: Hazuki Okabayashi, Tetsuya Tanaka, Ryuta Nakanishi, Masaitsu Nakajima, Keisuke Kaneko
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Patent number: 7594099Abstract: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.Type: GrantFiled: August 31, 2007Date of Patent: September 22, 2009Assignee: Panasonic CorporationInventors: Tetsuya Tanaka, Hazuki Okabayashi, Taketo Heishi, Hajime Ogawa, Tsuneyuki Suzuki, Tokuzo Kiyohara, Takeshi Tanaka, Hideshi Nishida, Masaki Maeda
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Patent number: 7555610Abstract: The cache memory in the present invention includes a C flag setting unit 40 which adds, to each cache entry holding line data, a cleaning flag C indicating whether or not a write operation will be performed hereafter, and a cleaning unit 39 which writes back, to the memory, line data of a cache entry that has been added with a cleaning flag C indicating that a write operation will not be performed, and has been set with a dirty flag D indicating that the cache entry has been written into.Type: GrantFiled: November 2, 2004Date of Patent: June 30, 2009Assignee: Panasonic CorporationInventors: Hazuki Okabayashi, Ryuta Nakanishi, Tetsuya Tanaka
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Publication number: 20090100231Abstract: A cache memory system which readily accepts software control for processing includes: a cache memory provided between a processor and memory; and a TAC (Transfer and Attribute Controller) for controlling the cache memory. The TAC receives a command which indicates a transfer and an attribute operation of cache data and a target for the operation, resulting from the execution of a predetermined instruction by the processor, so as to request the operation indicated by the command against the address to the cache memory.Type: ApplicationFiled: February 8, 2006Publication date: April 16, 2009Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Hazuki Okabayashi, Tetsuya Tanaka, Ryuta Nakanishi, Masaitsu Nakajima, Keisuke Kaneko
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Publication number: 20090077318Abstract: A cache memory of the present invention includes a second cache memory that is operated in parallel with a first cache memory, a judgment unit which, when a cache miss occurs in both of the first cache memory and the second cache memory, makes a true or false judgment relating to an attribute of data for which memory access resulted in the cache miss, and a controlling unit which stores memory data in the second cache memory when a judgment of true is made, and stores the memory data in the first cache memory when a judgment of false is made.Type: ApplicationFiled: March 17, 2006Publication date: March 19, 2009Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Takao Yamamoto, Tetsuya Tanaka, Ryuta Nakanishi, Masaitsu Nakajima, Keisuke Kaneko, Hazuki Okabayashi
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Patent number: 7502887Abstract: The cache memory in the present invention is an N-way set-associative cache memory including a control register which indicates one or more ways among N ways, a control unit which activates the way indicated by said control register, and an updating unit which updates contents of said control register. The control unit restricts at least replacement, for a way other than the active way indicated by the control register.Type: GrantFiled: September 8, 2004Date of Patent: March 10, 2009Assignee: Panasonic CorporationInventors: Tetsuya Tanaka, Hazuki Okabayashi, Ryuta Nakanishi, Tokuzo Kiyohara, Takao Yamamoto, Keisuke Kaneko
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Patent number: 7454575Abstract: The cache memory in the present invention is a cache entry having, in a correspondence with a cache entry which holds a data unit of caching, a valid flag indicating whether or not the cache entry is valid, and a dirty flag indicating whether or not the cache entry has been written into. The cache memory in the present invention includes an altering unit which, based on an instruction from a processor, sets, in the cache entry, an address serving as a tag and sets the valid flag, without loading data from a memory, or resets the dirty flag in a state in which the cache entry holds rewritten data that has not been written back.Type: GrantFiled: December 21, 2004Date of Patent: November 18, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Ryuta Nakanishi, Hazuki Okabayashi, Tetsuya Tanaka, Shuji Miyasaka
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Publication number: 20080209407Abstract: The present invention provides a processor which has a small-scale circuit and is capable of executing loop processing at a high speed while consuming a small amount of power. When the processor decodes an instruction “jloop C6,C1:C4,TAR,Ra”, the processor (i) sets a conditional flag C4 to 0 when the value of a register Ra is smaller than 0, (ii) moves the value of a conditional flag C2 to a conditional flag C1, moves the value of a conditional flag C3 to the conditional flag C2, and moves the value of the conditional flag C4 to the conditional flags C3 and C6, (iii) adds ?1 to the register Ra and stores the result into the register Ra, and (iv) branches to an address specified by a branch register (TAR). When not filled with a branch target instruction, the jump buffer will be filled with a branch target instruction.Type: ApplicationFiled: April 25, 2008Publication date: August 28, 2008Inventors: Hazuki Okabayashi, Tetsuya Tanaka, Taketo Heishi, Hajime Ogawa
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Publication number: 20080168232Abstract: A cache memory according to the present invention includes: a W flag setting unit (40) that modifies order data indicating an access order per cache entry that holds a data unit of a cache so as to reflect an actual access order; and a replace unit (39) that selects a cache entry for replacement based on the modified order data and replaces the cache entry.Type: ApplicationFiled: November 2, 2004Publication date: July 10, 2008Inventors: Hazuki Okabayashi, Ryuta Nakanishi, Tetsuya Tanaka, Shuji Miyasaka
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Patent number: 7380112Abstract: The present invention provides a processor which has a small-scale circuit and is capable of executing loop processing at a high speed while consuming a small amount of power. When the processor decodes an instruction “jloop C6,C1:C4,TAR,Ra”, the processor (i) sets a conditional flag C4 to 0 when the value of a register Ra is smaller than 0, (ii) moves the value of a conditional flag C2 to a conditional flag C1, moves the value of a conditional flag C3 to the conditional flag C2, and moves the value of the conditional flag C4 to the conditional flags C3 and C6, (iii) adds ?1 to the register Ra and stores the result into the register Ra, and (iv) branches to an address specified by a branch register (TAR). When not filled with a branch target instruction, the jump buffer will be filled with a branch target instruction.Type: GrantFiled: March 22, 2004Date of Patent: May 27, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hazuki Okabayashi, Tetsuya Tanaka, Taketo Heishi, Hajime Ogawa
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Publication number: 20080046688Abstract: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.Type: ApplicationFiled: August 31, 2007Publication date: February 21, 2008Inventors: Tetsuya Tanaka, Hazuki Okabayashi, Taketo Heishi, Hajime Ogawa, Tsuneyuki Suzuki, Tokuzo Kiyohara, Takeshi Tanaka, Hideshi Nishida, Masaki Maeda
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Publication number: 20080046690Abstract: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.Type: ApplicationFiled: August 31, 2007Publication date: February 21, 2008Inventors: Tetsuya Tanaka, Hazuki Okabayashi, Taketo Heishi, Hajime Ogawa, Tsuneyuki Suzuki, Tokuzo Kiyohara, Takeshi Tanaka, Hideshi Nishida, Masaki Maeda
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Publication number: 20080046704Abstract: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.Type: ApplicationFiled: August 31, 2007Publication date: February 21, 2008Inventors: Tetsuya Tanaka, Hazuki OKabayashi, Taketo Heishi, Hajime Ogawa, Tsuneyuki Suzuki, Tokuzo Kiyohara, Takeshi Tanaka, Hideshi Nishida, Masaki Maeda
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Publication number: 20080046687Abstract: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.Type: ApplicationFiled: August 31, 2007Publication date: February 21, 2008Inventors: Tetsuya Tanaka, Hazuki Okabayashi, Taketo Heishi, Hajime Ogawa, Tsuneyuki Suzuki, Tokuzo Kiyohara, Takeshi Tanaka, Hideshi Nishida, Masaki Maeda
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Patent number: 7281117Abstract: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.Type: GrantFiled: September 24, 2003Date of Patent: October 9, 2007Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Tetsuya Tanaka, Hazuki Okabayashi, Taketo Heishi, Hajime Ogawa, Tsuneyuki Suzuki, Tokuzo Kiyohara, Takeshi Tanaka, Hideshi Nishida, Masaki Maeda
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Publication number: 20070186048Abstract: The cache memory in the present invention includes a prediction unit 39 which predicts, based on the progress of the memory access outputted from the memory, a line address which should be prefetched next.Type: ApplicationFiled: March 16, 2005Publication date: August 9, 2007Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Ryuta Nakanishi, Hazuki Okabayashi, Tetsuya Tanaka, Tokuzo Kiyohara
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Publication number: 20070143548Abstract: The cache memory in the present invention is a cache entry having, in a correspondence with a cache entry which holds a data unit of caching, a valid flag indicating whether or not the cache entry is valid, and a dirty flag indicating whether or not the cache entry has been written into. The cache memory in the present invention includes an altering unit which, based on an instruction from a processor, sets, in the cache entry, an address serving as a tag and sets the valid flag, without loading data from a memory, or resets the dirty flag in a state in which the cache entry holds rewritten data that has not been written back.Type: ApplicationFiled: December 21, 2004Publication date: June 21, 2007Inventors: Ryuta Nakanishi, Hazuki Okabayashi, Tetsuya Tanaka, Shuji Miyasaka