Abstract: The cache memory in the present invention includes a C flag setting unit 40 which adds, to each cache entry holding line data, a cleaning flag C indicating whether or not a write operation will be performed hereafter, and a cleaning unit 39 which writes back, to the memory, line data of a cache entry that has been added with a cleaning flag C indicating that a write operation will not be performed, and has been set with a dirty flag D indicating that the cache entry has been written into.

Abstract: A processor according to the present invention includes a decoding unit, an operation unit and others. When the decoding unit decodes an instruction “vxaddh Rc, Ra, Rb”, an arithmetic and logic/comparison operation unit and others (i) adds the higher 16 bits of a register Ra to the lower 16 bits of the register Rb, stores the result in the higher 16 bits of a register Rc, and in parallel with this, (ii) adds the lower 16 bits of the register Ra to the higher 16 bits of the register Rb, and stores the result in the lower 16 bits of the register Rc.

Abstract: The data processing apparatus capable of efficiently using a cache memory includes: a cache memory 28 and a memory 30 that stores an instruction or data in each area specified by a physical address; an arithmetic processing unit 22 that outputs a logical address including the physical address and process determining data indicating a prescribed process, obtains the instruction or the data corresponding to the physical address included in the logical address, and execute the instruction; an address conversion unit 26 that converts the logical address outputted by the arithmetic processing unit 22 into the physical address. The data processing apparatus reads the instruction or the data stored in areas specified by the physical address, in the cache memory 28 and the memory 30, and executes a prescribed process based on the process determining data.

Abstract: When the processor, which has a small-scale circuit and is capable of executing loop processing at high speed consuming a small amount of power, decodes Instruction “jloop C6,C1:C4,TAR,Ra”, the processor (i) sets a conditional flag C4 to 0 when the value of a register Ra is smaller than 0, (ii) moves the value of a conditional flag C2 to a conditional flag C1, moves the value of a conditional flag C3 to the conditional flag C2, and moves the value of the conditional flag C4 to the conditional flags C3 and C6, (iii) adds −1 to the register Ra and stores the result into the register Ra, and (iv) branches to an address specified by a branch register (TAR). When not filled with a branch target instruction, the jump buffer will be filled with a branch target instruction.

Abstract: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes an instruction “vxaddh Rc, Ra, Rb”, an arithmetic and logic/comparison operation unit 41 and others (i) adds the higher 16 bits of a register Ra to the lower 16 bits of the register Rb, stores the result in the higher 16 bits of a register Rc, and in parallel with this, (ii) adds the lower 16 bits of the register Ra to the higher 16 bits of the register Rb, and stores the result in the lower 16 bits of the register Rc.

Abstract: A processor according to the present invention includes a decoding unit 20, an operation unit 40 and others. When the decoding unit 20 decodes Instruction vcchk, the operation unit 40 and the like judges whether vector condition flags VC0˜VC3 (110) of a condition flag register (CFR) 32 are all zero or not, and (i) sets condition flags C4 and C5 of the condition flag register (CFR) 32 to 1 and 0, respectively, when all of the vector condition flags VC0˜VC3 are zero, and (ii) sets the condition flags C4 and C5 to 0 and 1, respectively, when not all the vector condition flags are zero. Then, the vector condition flags VC0˜VC3 are stored in the condition flags C0˜C3.