Abstract: A coaxial connector includes: a shell integrally formed as a unitary piece; and an insulator and a conductive contact retained to the insulator, the contact having an upper contacting portion and a lower contacting portion extending out of the insulator, wherein the shell includes a first mating tube opening upwards, a second mating tube opening upward and disposed in the first mating tube, a receiving cavity opening downward, and a third mating tube disposed in the receiving space, the insulator is assembled and fixed in the shell, and the upper contacting portion is exposed to the second mating tube and the lower contacting portion is exposed to the third mating tube.

Abstract: A semiconductor device is provided. The semiconductor device includes a base layer having a first side for forming memory cells and a second side that is opposite to the first side. The semiconductor device includes a stack of alternating word line layers and insulating layers that is positioned over the first side of the base layer, where the stack includes a first region and a second region. A channel structure extends through the first region of the stack in a vertical direction and further extends into the base layer from the first side. A plurality of connection structures are formed over the second side of the base layer and include a first connection structure that is coupled to the channel structure.

Abstract: A connector and an electronic device, to resolve a problem of poor mountability of the connector. The connector includes a housing, a conductive core, and a fastening structure. The housing has a channel that passes through a first end and a second end of the housing. The conductive core is disposed in the channel. A solder leg is disposed on one end of the conductive core, and the solder leg protrudes from the first end of the housing and is configured to be soldered to a circuit board. The fastening structure is configured to fasten the housing to a panel. The conductive core may be directly soldered to the circuit board, so that a connection effect between the conductive core and the circuit board can be improved, and mounting steps can be reduced.

Abstract: Disclosed are Hematopoietic Progenitor Kinase 1 (HPK1) degradation/disruption compounds including a HPK1 ligand, a degradation/disruption tag and a linker, and methods for use of such compounds in the treatment of HPK1-mediated diseases.

Abstract: A dual-person dual-machine measurement method for mining and transportation equipment is provided, including an intelligent measurement module, a measurement user module, and a measurement task module. The intelligent measurement module includes two inspectors conducting inspections in opposite directions and Augmented Reality (AR) glasses carried by the inspectors, and is configured to collect data based on Hololens equipment. The measurement user module is built into edge computers carried by the inspectors and includes a multi-user collaborative platform, where the multi-user collaborative platform measures working-face mining-transportation pose data under AR assistance and performs data processing operations, and the multi-user collaborative platform enables real-time collaboration of measurement perspectives and data among multiple users.

Abstract: A semiconductor device, a memory, and a memory system are provided. The semiconductor device comprises an array device and a plurality of source leading-out contacts, and the array device comprises a plurality of channel structures and a source layer connected with the plurality of channel structures. The plurality of source leading-out contacts are connected with the source layer, and the plurality of source leading-out contacts and the plurality of channel structures are located on two sides of the source layer, respectively, and orthographic projections of the plurality of source leading-out contacts on the source layer are evenly spaced.

Abstract: Methods, devices, systems, and techniques for managing structure leakage in semiconductor devices are provided. In one aspect, a semiconductor device includes memory cells. Each memory cell includes a transistor having a semiconductor body and a gate structure. Gate structures of transistors of two adjacent memory cells extend along a first direction in a first trench structure. The semiconductor body includes first and second terminals at opposite ends of the semiconductor body along the first direction. The semiconductor device further includes a diffusion region including a first diffusion portion, a second diffusion portion, and a middle portion along the first direction. The diffusion region surrounds a first end of the first trench structure. A first area of the first trench structure surrounded by the first diffusion portion is greater than a second area of the first trench structure surrounded by the middle diffusion portion and the second diffusion portion.

Abstract: A semiconductor device, a memory device, and a memory system are provided. The semiconductor device includes an array device and source leading-out contacts. The array device includes channel structures and a source layer connected with the channel structures. The source leading-out contacts are connected with the source layer. The source leading-out contacts and the channel structures are located on two sides of the source layer, respectively. Orthographic projections of the source leading-out contacts on the source layer are in evenly spaced distribution.

Abstract: Disclosed are Hematopoietic Progenitor Kinase 1 (HPK1) degradation/disruption compounds including a HPK1 ligand, a degradation/disruption tag and a linker, and methods for use of such compounds in the treatment of HPK1-mediated diseases.

Abstract: A semiconductor memory device includes trench isolations arranged in a bit-line direction, gate structures arranged in a word-line direction perpendicular to the bit-line direction, an array of vertical-transistor channels arranged in a vertical direction perpendicular to the bit-line direction and the word-line direction and separated by the trench isolations and gate structures, top ends of the array of the vertical-transistor channels in each column being connected to a line of semiconductor structure extending in the bit-line direction at a backside of the semiconductor memory device, and air gap tunnels along the word-line direction that each crosses below the line of semiconductor structure and between two neighboring vertical-transistor channels in a first region at the backside of the semiconductor memory device.

Abstract: An electrical connector includes: a main shell having a receiving cavity going through a front end and a rear end thereof; a conductive assembly received in the receiving cavity and comprising an inner conductor, an outer conductor, and a cable electrically connected with the inner conductor and the outer conductor; and a limiting member; wherein the main shell has plural elastic arms extending rearward in the receiving cavity and each elastic arm has a hook, the conductive assembly has a fixing member radiating therearound, the hooks abut forwards against a rear face of the fixing member, and the limiting member is sandwiched between the elastic arms and an inside of the receiving cavity.

Abstract: Implementations of the present application provide a semiconductor device, a fabrication method and a memory system. The semiconductor device includes a plurality of semiconductor pillars arranged in an array and a word line structure. The plurality of semiconductor pillars extend along a first direction and include at least one side face, wherein the plurality of semiconductor pillars are arranged in rows along a second direction perpendicular to the first direction. The word line structure is located between a first row and a second row of semiconductor pillars that are adjacent, and includes a first word line structure and a second word line structure spaced apart from the first word line structure, wherein the first word line structure is connected with a side face of the first row of semiconductor pillars, and the second word line structure is connected with a side face of the second row of semiconductor pillars.

Abstract: An elbow cable connector includes: a cable assembly comprising a head, an outer conductor extending forwards, an insulator received in the outer conductor, an inner conductor received in the insulator, a cable mechanically connected with the inner conductor and extending downwards, and a rear cover; and an outer shell surrounding the outer conductor, the head, and an upper end of the cable; wherein the head is of a die casting and has a fixing hole running forwards and a receiving groove opening rearwards and downwards, the outer conductor has a rear flange on a rear end thereof, the outer conductor goes across the fixing hole and the rear flange presses against a front face of the receiving groove, a rear part of the insulator and the upper end of the cable are received in the receiving groove, and the rear cover presses forward and seal the receiving groove.

Abstract: Disclosed are a method and an apparatus for optimizing and testing a harness layout of a battery swapping electrical interface. The method includes: obtaining a first distance, a second distance and initial floating data of the battery swapping electrical interface; adjusting the first distance and the second distance to obtain first floating data of the battery swapping electrical interface again; repeatedly inserting or pulling the plug into or out of the socket of the battery swapping electrical interface; obtaining second floating data of the battery swapping electrical interface after repeatedly inserting or pulling the plug into or out of the socket for a preset number of times; and determining the current first distance and second distance as optimal distances if it is judged that the second floating data is in the second index interval.

Abstract: Disclosed are three-dimensional (3D) memory devices and fabricating methods thereof. In some embodiments, a disclosed memory device comprises a wafer structure having a sealing region and a chip region. The wafer structure comprises a substrate, a memory string array on a first side of the substrate in the chip region, a first protection structure and a second protection structure on the first side of the substrate in the sealing region, and a first contact and a second contact extending through the substrate in the sealing region. The first contact is in contact with the first protection structure, and the second contact is in contact with the second protection structure.

Abstract: Disclosed are three-dimensional (3D) memory devices and fabricating methods thereof. In some embodiments, a disclosed memory device comprises a wafer structure having a sealing region and a chip region. The wafer structure comprises a substrate, a memory string array on a first side of the substrate in the chip region, a first protection structure and a second protection structure on the first side of the substrate in the sealing region, and a first contact and a second contact extending through the substrate in the sealing region. The first contact is in contact with the first protection structure, and the second contact is in contact with the second protection structure.

Abstract: Examples of the present application provide a semiconductor device, a memory system and a fabrication method of a semiconductor device. The semiconductor device includes: a silicon contact structure; a metal silicide layer on one side of the silicon contact structure; a bit line structure located on the side of the metal silicide layer away from the silicon contact structure and extending in a first direction; and a sidewall structure covering the opposite sides of the bit line structure and the opposite sides of the metal silicide layer in the first direction and extending further to cover the opposite sides, in the first direction, of the first end of the silicon contact structure proximate to the metal silicide layer.

Abstract: A board connector includes: a metal housing having a base portion, four mating tubes opening forward, and four receiving grooves opening through a rear face and a bottom face of the base portion and communicating with corresponding mating tubes; four terminal assemblies received and retained in corresponding receiving grooves; and a rear plate, wherein the base portion of the metal housing has a rear guiding slot and a supporting portion at each side wall thereof, the supporting portions extend horizontally, the rear plate slides into the rear guiding slots from the bottom face, and the supporting portions block a bottom face of the rear plate from moving downwardly.

Abstract: A board coaxial connector includes: a first insulator, a first inner conductor retained in the first insulator and having a mating portion and a first connecting portion extending out of the first insulator, a first outer conductor having a third connecting portion and retaining the first insulator, a second outer conductor mounted on the circuit board and having a fourth connecting portion, and a second inner conductor having a second connecting portion and a tail portion mounting on the circuit board, wherein the first connecting portion is connected with the second connecting portion, the third connecting portion is connected with the fourth connecting portion, and the first connecting portion of the first inner conductor is movable to slightly deviate from an axis of the second inner conductor.

Abstract: A farmland reference crop evapotranspiration prediction method based on uncertainty of meteorological factors, includes: S1. acquiring a set number of groups of weather forecast data of a prediction region within a preset time period; S2. inputting each group of weather forecast data into a Bayesian probability forecast system to obtain corrected weather forecast data; and S3. inputting each group of the corrected weather forecast data into a trained RBF neural network, and predicting to obtain a farmland reference crop evapotranspiration. In the present invention, the Bayesian probability forecast system is configured to correct the weather forecast data and eliminate uncertainty of weather forecast data to obtain the accurate reference crop evapotranspiration forecasted by the RBF neural network using these data.