Patents by Inventor He Chen

He Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240210911
    Abstract: A mold state monitoring system is provided, and the monitoring method thereof is: dividing multiple processing signals of a mold into initial state information and wear state information, so as to obtain a target model and a wear threshold based on the initial state information, and input the wear state information into the target model to obtain a wear index of the mold; inputting the latest multiple processing signals and corresponding wear indices thereof into a time series prediction model for training to obtain wear prediction values of hypothetical times, and then performing a predicting operation based on the wear prediction value, so that when the wear prediction value is greater than the wear threshold, it can be estimated as a damage time point of the mold. Therefore, via the design of the time series prediction model, the target information can be changed at any time on the production line, and the state of the mold can be monitored online in real time.
    Type: Application
    Filed: December 21, 2022
    Publication date: June 27, 2024
    Inventors: Yu-Hung PAI, Hung-Tsai WU, He-Chen LIAO, Kai-Jhih YANG
  • Publication number: 20240196589
    Abstract: A method of forming a memory device including providing a base wafer that includes a substrate, an insulation layer over the substrate, a sacrificial layer over the insulation layer, and a plurality of channel layers embedded in the sacrificial layer and the insulation layer, forming a plurality of grooves in the sacrificial layer each exposing a portion of the insulation layer and separating two adjacent rows of the channel layers, filling the plurality of grooves with an insulation material to form a plurality of spacers, removing the sacrificial layer to form a plurality of trenches that expose portions of the insulation layer and a portion of a sidewall of each of the channel layers, and forming a plurality of gate layers in the trenches.
    Type: Application
    Filed: December 15, 2022
    Publication date: June 13, 2024
    Inventors: He CHEN, Ziqun HUA, Hongbin ZHU
  • Publication number: 20240188275
    Abstract: A method of forming a memory device including providing a base wafer including a semiconductor material layer, and forming first and second spacers in the semiconductor material layer. The first spacers extend from a first surface of the semiconductor material layer to a second surface of the semiconductor material layer. The second spacers cross the first spacers and extend from the first surface of the semiconductor material layer to a position inside the semiconductor material layer. A plurality of semiconductor material strips are formed each between bottoms of the second spacers and the second surface of the semiconductor material layer and sandwiched between two neighboring first spacers. The method further includes performing a silicidation process at the second surface of the semiconductor material layer to convert at least portion of each of the semiconductor material strips into a silicide layer.
    Type: Application
    Filed: December 15, 2022
    Publication date: June 6, 2024
    Inventors: He CHEN, Ziqun HUA
  • Patent number: 11989264
    Abstract: An automatic generation system of a training image and a method thereof are provided. The disclosure generates a training image and records the target category and the target position. The disclosure adds the target image to the container image as a candidate image, calculates a reliability of the candidate image, and repeatedly executes the process until the reliability of the candidate image meets a threshold condition for generating the training image. The disclosure is able to generate the training images automatically, and the recognition difficulty of the training image is adjustable by the user, so as to be suitable for customized recognition training.
    Type: Grant
    Filed: June 2, 2023
    Date of Patent: May 21, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Tien-He Chen, Che-Min Chen, Jia-Wei Yan
  • Publication number: 20240131173
    Abstract: Transcription factors (TFs) represent a major class of therapeutic targets for the treatment of human diseases including cancer. Although the biological function and even crystal structure of many TFs have been clearly elucidated, there is still no viable approach to target the majority of TFs, thus rendering them undruggable for decades. PROTACs (PROteolysis TArgeting Chimeras) have emerged as a powerful tool for the pharmaceutical development since the effect of PROTACs largely relies on engineered protein-protein interaction to aid the degradation of targets by the ubiquitin-proteasome system (UPS). The present disclosure provides a DNA-PROTAC platform for targeted degraders of individual TFs of interest. These DNA based Transcription Factor targetting PROTACS (or “TF-PROTACS”) may provide specificity to TF degradation based on the conserved DNA-binding motifs of respective TFs.
    Type: Application
    Filed: November 27, 2023
    Publication date: April 25, 2024
    Applicants: Beth Israel Deaconess Medical Center, Inc., Icahn School of Medicine at Mount Sinai
    Inventors: Wenyi WEI, Jian JIN, Jing LIU, He CHEN, Husnu Ümit KANISKAN
  • Publication number: 20240129606
    Abstract: The disclosure provides an image capturing method performed by applying a plurality of detection devices to perform an image capturing operation. The image capturing method includes following steps: A first detection device is provided. A second detection device is provided and connected to the first detection device. An image capturing operation is performed by the first detection device and the second detection device, so as to generate first image data and second image data, respectively. The second image data are transferred to the first detection device by the second detection device. By applying the image capturing method, costs of a detection system are not significantly increased, and the detection devices may be expanded.
    Type: Application
    Filed: September 3, 2023
    Publication date: April 18, 2024
    Applicant: InnoCare Optoelectronics Corporation
    Inventor: Yu-Heing Chen
  • Patent number: 11956958
    Abstract: Methods for forming a semiconductor device are disclosed. According to some aspects, a first implantation is performed on a first of a first semiconductor structure to form a buried stop layer in the first substrate. A second semiconductor device is formed. The first semiconductor structure and the second semiconductor device are bonded. The first substrate is thinned and the buried stop layer is removed, and an interconnect layer is formed above the thinned first substrate.
    Type: Grant
    Filed: April 22, 2021
    Date of Patent: April 9, 2024
    Assignee: YANGTZE MEMORY TECHNOLOGIES CO., LTD.
    Inventor: He Chen
  • Publication number: 20240049455
    Abstract: A semiconductor device includes an array of memory cells, bit lines coupled to the memory cells, and first air gaps. Each of the memory cells includes a vertical transistor. The vertical transistor includes a semiconductor body extends in a first direction. Each of the bit lines is electrically connected to a first end of the semiconductor body. At least one of the first air gaps is between adjacent bit lines.
    Type: Application
    Filed: July 24, 2023
    Publication date: February 8, 2024
    Inventors: Mingliang Xu, He Chen, Wei Liu
  • Publication number: 20240043328
    Abstract: Disclosed are a reusable freely-shapable eco-friendly recycled brick manufacturing process and its product. The manufacturing process includes the steps of: (S1): preparing a raw material of a calcium silicate board; (S2): preparing a raw material of a gypsum board, mixing it with the raw material of the calcium silicate board obtained in (S1) and crushing them into fine powder; (S3): preparing a raw cement and mix it with the fine powder obtained in (S2); (S4): preparing raw water and mix it with the mixture obtained in (S3); (S5): preparing an enhancer and mix it with the mixture obtained in (S4), wherein the enhancer includes little surfactant and adhesive; (S): uniformly mix the raw materials prepared according to the eco-friendly recycled brick manufacturing process and their proportion, and pouring them into at least one mold; and (S7): forming the eco-friendly recycled brick product.
    Type: Application
    Filed: July 31, 2023
    Publication date: February 8, 2024
    Inventors: Jhong-He CHEN, Bo-Heng CHEN, Li-Ying CHEN
  • Publication number: 20230386985
    Abstract: A semiconductor structure includes a solder resist layer disposed on a circuit substrate and partially covering contact pads of the circuit substrate, and external terminals disposed on the solder resist layer and extending through the solder resist layer to land on the contact pads. The external terminals include a first external terminal and a second external terminal which have different heights. A first interface between the first external terminal and corresponding one of the contact pads underlying the first external terminal is less than a second interface between the second external terminal and another corresponding one of the contact pads underlying the second external terminal.
    Type: Application
    Filed: July 26, 2023
    Publication date: November 30, 2023
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Yu Yeh, Cing-He Chen, Kuo-Chiang Ting, Weiming Chris Chen, Chia-Hao Hsu, Kuan-Yu Huang, Shu-Chia Hsu
  • Patent number: 11829715
    Abstract: The present invention provides text-based news significance evaluation methods, apparatuses, and electronic devices for improving efficiency and accuracy of news significance evaluation, and implementing real-time dynamic evaluation on text news. The method comprises: reading text news; preprocessing the text news to obtain original data; extracting feature values from the original data, which comprises metadata, a keyword, and a probability model feature value; and obtaining a score of each feature value according to a weight ratio corresponding to each feature value. The apparatus comprises: a text news reading module, a text news preprocessing module, a feature value extraction module, a feature value weight determining module, and a text news significance evaluation module. The electronic device comprises a memory and a processor. The memory stores a computer program that can run on the processor.
    Type: Grant
    Filed: January 10, 2021
    Date of Patent: November 28, 2023
    Assignee: Business Management Advisory LLC
    Inventors: Qingquan Zhang, Wenxi Lu, He Chen, Ying Wu
  • Publication number: 20230380142
    Abstract: A three-dimensional (3D) memory device and a fabricating method thereof are disclosed. The 3D memory device can comprise an array of memory cells. Each memory cell can comprise a capacitor and a vertical transistor. The vertical transistor can comprise a semiconductor body extending in a vertical direction and in contact with the capacitor, and a three-sided gate structure surrounding the semiconductor body from three lateral directions. The 3D memory device can further comprise a memory controller configured to control the array of memory cells.
    Type: Application
    Filed: May 16, 2023
    Publication date: November 23, 2023
    Inventors: He Chen, Ziqun Hua, Yanhong Wang, Wei Liu
  • Publication number: 20230371244
    Abstract: A three-dimensional memory device having vertical transistors and a method for forming the same are disclosed. In an example, the memory device includes an array of memory cells each including a vertical transistor. Along a first direction, one of the vertical transistors is arranged between two of separation structures in a plan view. Each of the separation structures includes a protrusion, and the separation structure and a corresponding protrusion are integral. The memory device also includes a plurality of bit lines that include at least one conductive layer. The at least one conductive layer is arranged between two protrusions of the two separation structures and on the one of vertical transistors to couple one of the bit lines with the one of the vertical transistors.
    Type: Application
    Filed: May 15, 2023
    Publication date: November 16, 2023
    Inventors: He Chen, Ziqun Hua
  • Publication number: 20230364243
    Abstract: PROTACs (PROteolysis TArgeting Chimeras) are an emerging class of promising therapeutic modalities that degrade intracellular protein targets by hijacking the cellular ubiquitin-proteasome system. However, potential toxicity of PROTACs in normal cells due to off-tissue on-target degradation effect limits their clinical applications. Precise control of PROTAC's on-target degradation activity in a tissue selective manner could minimize potential toxicity/side-effects. To this end, we developed a cancer cell selective delivery strategy for PROTACs by conjugating a folate group to ubqiquitin recruitment moiety to achieve targeted degradation of proteins of interest (POIs) in cancer cells versus normal cells. We show that our folate-PROTACs, including BRD PROTAC (Folate-ARV-771), MEK PROTAC (Folate-MS432) and ALK PROTAC (Folate-MS99, Folate-S2-MS4048) are capable of degrading BRDs, MEKs and ALK, respectively, in a folate receptor-dependent manner.
    Type: Application
    Filed: July 31, 2023
    Publication date: November 16, 2023
    Applicants: Beth Israel Deaconess Medical Center, Inc., Icahn School of Medicine at Mount Sinai
    Inventors: Wenyi WEI, Jian JIN, Husnu Ümit KANISKAN, He CHEN, Jing LIU
  • Publication number: 20230335521
    Abstract: A semiconductor device is provided. The semiconductor device includes a base layer having a first side for forming memory cells and a second side that is opposite to the first side. The semiconductor device includes a stack of alternating word line layers and insulating layers that is positioned over the first side of the base layer, where the stack includes a first region and a second region. A channel structure extends through the first region of the stack in a vertical direction and further extends into the base layer from the first side. A plurality of connection structures are formed over the second side of the base layer and include a first connection structure that is coupled to the channel structure.
    Type: Application
    Filed: June 23, 2023
    Publication date: October 19, 2023
    Applicant: Yangtze Memory Technologies Co., Ltd.
    Inventors: He CHEN, Liang XIAO
  • Publication number: 20230306080
    Abstract: An automatic generation system of a training image and a method thereof are provided. The disclosure generates a training image and records the target category and the target position. The disclosure adds the target image to the container image as a candidate image, calculates a reliability of the candidate image, and repeatedly executes the process until the reliability of the candidate image meets a threshold condition for generating the training image. The disclosure is able to generate the training images automatically, and the recognition difficulty of the training image is adjustable by the user, so as to be suitable for customized recognition training.
    Type: Application
    Filed: June 2, 2023
    Publication date: September 28, 2023
    Inventors: Tien-He CHEN, Che-Min CHEN, Jia-Wei YAN
  • Patent number: 11728303
    Abstract: A semiconductor device is provided. The semiconductor device includes a base layer having a first side for forming memory cells and a second side that is opposite to the first side. The semiconductor device includes a stack of alternating word line layers and insulating layers that is positioned over the first side of the base layer, where the stack includes a first region and a second region. A channel structure extends through the first region of the stack in a vertical direction and further extends into the base layer from the first side. A plurality of connection structures are formed over the second side of the base layer and include a first connection structure that is coupled to the channel structure.
    Type: Grant
    Filed: January 14, 2021
    Date of Patent: August 15, 2023
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: He Chen, Liang Xiao
  • Patent number: 11728238
    Abstract: A semiconductor package includes a redistribution structure, at least one semiconductor device and a plurality of heat dissipation films. The at least one semiconductor device is mounted on the redistribution structure. The plurality of heat dissipation films are disposed on the at least one semiconductor device in a side by side manner and jointly cover an upper surface of the at least one semiconductor device. A manufacturing method of the semiconductor package is also provided.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: August 15, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ting-Yu Yeh, Cing-He Chen, Kuo-Chiang Ting, Weiming Chris Chen, Chia-Hao Hsu
  • Patent number: 11709913
    Abstract: An automatic generation system of a training image and a method thereof are provided. The disclosure generates a training image and records the target category and the target position. The disclosure adds the target image to the container image as a candidate image, calculates a reliability of the candidate image, and repeatedly executes the process until the reliability of the candidate image meets a threshold condition for generating the training image. The disclosure is able to generate the training images automatically, and the recognition difficulty of the training image is adjustable by the user, so as to be suitable for customized recognition training.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: July 25, 2023
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Tien-He Chen, Che-Min Chen, Jia-Wei Yan
  • Patent number: 11710730
    Abstract: A fabricating method of a semiconductor device is provided. A temporary semiconductor structure is provided. The temporary semiconductor structure includes a temporary substrate and a conductive layer, the temporary substrate has a first surface, the conductive layer is disposed on the first surface of the temporary substrate, and the conductive layer includes one or more first trace. Then, a recess is formed in the temporary semiconductor structure to form a first semiconductor structure and a first substrate. The recess penetrates through the first substrate and expose the one or more first trace. Thereafter, an input/output pad is formed in the recess and on the one or more first trace.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: July 25, 2023
    Assignee: Yangtze Memory Technologies Co., Ltd.
    Inventors: He Chen, Zi Qun Hua, Shu Wu, Yong Qing Wang, Liang Xiao