Patents by Inventor He Lin
He Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20150168498Abstract: A method and a system for estimating the State of Health (SOH) of a battery set are disclosed. The method utilizes a discrete quantization algorithm to estimate the SOH of the battery set, wherein the voltage standard deviations are calculated according to the loop voltages of the battery cells, and comparing the rated discharge capacity with the voltage standard deviations for estimating the SOH of the battery set.Type: ApplicationFiled: December 16, 2013Publication date: June 18, 2015Applicant: Automotive Research & Testing CenterInventors: Bo-Han HWANG, Kuo-Liang WENG, Deng-He LIN
-
Publication number: 20150028820Abstract: An activate circuit for an electronic device includes a first node, a first transistor including a source coupled to a ground, a drain coupled to the first node, and a gate coupled to a battery voltage, a first diode including an anode coupled to an activate signal, and a cathode a first resistance coupled between the cathode of the first diode and the first node, a capacitor coupled between the first node and the ground having a logic low level, and a second transistor including a source coupled to the ground, a drain coupled to the activate signal, and a gate coupled to the first node.Type: ApplicationFiled: September 6, 2013Publication date: January 29, 2015Applicant: Wistron CorporationInventors: Jia-He Lin, Chun-Ta Lee
-
Publication number: 20140358830Abstract: A hotspot detection system that classifies a set of hotspot training data into a plurality of hotspot clusters according to their topologies, where the hotspot clusters are associated with different hotspot topologies, and classifies a set of non-hotspot training data into a plurality of non-hotspot clusters according to their topologies, where the non-hotspot clusters are associated with different topologies. The system extracts topological and non-topological critical features from the hotspot clusters and centroids of the non-hotspot clusters. The system also creates a plurality of kernels configured to identify hotspots, where each kernel is constructed using the extracted critical features of the non-hotspot clusters and the extracted critical features from one of the hotspot clusters, and each kernel is configured to identify hotspot topologies different from hotspot topologies that the other kernels are configured to identify.Type: ApplicationFiled: May 27, 2014Publication date: December 4, 2014Applicant: Synopsys, Inc.Inventors: Charles C. Chiang, Yen-Ting Yu, Geng-He Lin, Hui-Ru Jiang
-
Patent number: 8872543Abstract: A configurable logic block (CLB) and an operation method of the CLB are provided. The CLB includes memory units and a selecting circuit. The memory unit includes a first resistive non-volatile memory (RNVM) element and a second RNVM element. Top electrodes (TEs) of the first and second RNVM elements are coupled to an output terminal of the memory unit. Bottom electrodes (BEs) of the first and second RNVM elements are respectively coupled to a first bias terminal and a second bias terminal of the memory unit. The selecting circuit selects one of the memory units according to an input logic value and determines an output logic value of the CLB according to an output logic value of the selected memory unit.Type: GrantFiled: April 29, 2013Date of Patent: October 28, 2014Assignee: Industrial Technology Research InstituteInventors: Wen-Pin Lin, Chih-He Lin, Shyh-Shyuan Sheu, Hsin-Chi Lai
-
Patent number: 8823415Abstract: A logic gate including a first resistive non-volatile memory device and a second resistive non-volatile memory device is provided. When top electrodes of the first and the second resistive non-volatile memory devices are coupled to an output terminal of the logic gate, bottom electrodes of the first and the second resistive non-volatile memory devices are respectively coupled to a first input terminal and a second input terminal of the logic gate. When the bottom electrodes of the first and the second resistive non-volatile memory devices are coupled to the output terminal of the logic gate, the top electrodes of the first and the second resistive non-volatile memory devices are respectively coupled to the first input terminal and the second input terminal of the logic gate.Type: GrantFiled: October 4, 2012Date of Patent: September 2, 2014Assignee: Industrial Technology Research InstituteInventors: Wen-Pin Lin, Chih-He Lin, Yu-Sheng Chen, Zhe-Hui Lin
-
Publication number: 20140210514Abstract: A configurable logic block (CLB) and an operation method of the CLB are provided. The CLB includes memory units and a selecting circuit. The memory unit includes a first resistive non-volatile memory (RNVM) element and a second RNVM element. Top electrodes (TEs) of the first and second RNVM elements are coupled to an output terminal of the memory unit. Bottom electrodes (BEs) of the first and second RNVM elements are respectively coupled to a first bias terminal and a second bias terminal of the memory unit. The selecting circuit selects one of the memory units according to an input logic value and determines an output logic value of the CLB according to an output logic value of the selected memory unit.Type: ApplicationFiled: April 29, 2013Publication date: July 31, 2014Applicant: Industrial Technology Research InstituteInventors: Wen-Pin Lin, Chih-He Lin, Shyh-Shyuan Sheu, Hsin-Chi Lai
-
Patent number: 8718852Abstract: A self-learning regenerative braking control module is adapted for use with a vehicle, and includes a driving mode determining unit, an analyzing unit, and a regenerative braking determining unit. The driving mode determining unit determines a driving mode according to an accelerator signal, a brake signal, and a speed signal from the vehicle and outputs a coasting duration and coasting information associated with the driving mode to the analyzing unit for obtaining acceleration information. The regenerative braking determining unit obtains target regenerative braking data containing target vehicle speeds that vary with time based upon the acceleration information and regenerative braking reference data stored therein.Type: GrantFiled: December 26, 2012Date of Patent: May 6, 2014Assignee: Automotive Research & Testing CenterInventors: Kuo-Liang Weng, Chien-An Chen, Deng-He Lin, Ming-Chih Lin
-
Publication number: 20140122466Abstract: An data search apparatus includes: a storage unit, storing a plurality of data; an input unit, inputting a data name, selecting a plurality of preference sets, and inputting a grading set by a user; a process unit, receiving the data name for searching for a plurality of candidate data from the data stored in a storage unit and generating a ranking result.Type: ApplicationFiled: March 15, 2013Publication date: May 1, 2014Applicant: Quanta Computer Inc.Inventors: Tien-Chin Fang, Ching-Yu Tsai, Chih-Ling Liu, Ming-Jen Chen, Ching-Wen Lin, Chia-Hung Lin, Chen-Chung Lee, Chun-He Lin
-
Publication number: 20140115243Abstract: A resistive random-access memory device includes a memory array, a read circuit, a write-back logic circuit and a write-back circuit. The read circuit reads the data stored in a selected memory cell and accordingly generates a first control signal. The write-back logic circuit generates a write-back control signal according to the first control signal and a second control signal. The write-back circuit performs a write-back operation on the selected memory cell according to the write-back control signal and a write-back voltage, so as to change a resistance state of the selected memory cell from a low resistance state to a high resistance state, and generates the second control signal according to the resistance state of the selected memory cell.Type: ApplicationFiled: August 22, 2013Publication date: April 24, 2014Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chih-He Lin, Sih-Han Li, Wen-Pin Lin, Shyh-Shyuan Sheu
-
Publication number: 20140081498Abstract: A self-learning regenerative braking control module is adapted for use with a vehicle, and includes a driving mode determining unit, an analyzing unit, and a regenerative braking determining unit. The driving mode determining unit determines a driving mode according to an accelerator signal, a brake signal, and a speed signal from the vehicle and outputs a coasting duration and coasting information associated with the driving mode to the analyzing unit for obtaining acceleration information. The regenerative braking determining unit obtains target regenerative braking data containing target vehicle speeds that vary with time based upon the acceleration information and regenerative braking reference data stored therein.Type: ApplicationFiled: December 26, 2012Publication date: March 20, 2014Applicant: AUTOMOTIVE RESEARCH & TESTING CENTERInventors: Kuo-Liang Weng, Chien-An Chen, Deng-He Lin, Ming-Chih Lin
-
Publication number: 20140035620Abstract: A logic gate including a first resistive non-volatile memory device and a second resistive non-volatile memory device is provided. When top electrodes of the first and the second resistive non-volatile memory devices are coupled to an output terminal of the logic gate, bottom electrodes of the first and the second resistive non-volatile memory devices are respectively coupled to a first input terminal and a second input terminal of the logic gate. When the bottom electrodes of the first and the second resistive non-volatile memory devices are coupled to the output terminal of the logic gate, the top electrodes of the first and the second resistive non-volatile memory devices are respectively coupled to the first input terminal and the second input terminal of the logic gate.Type: ApplicationFiled: October 4, 2012Publication date: February 6, 2014Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Wen-Pin Lin, Chih-He Lin, Yu-Sheng Chen, Zhe-Hui Lin
-
Patent number: 8625361Abstract: A circuit and a method for controlling the write timing of a non-volatile memory are provided. The method includes the following steps. First, a resistance state switching of at least one memory cell of the non-volatile memory executing a writing operation is monitored to output a control signal. The memory cell stores data states with different resistance states. A write timing is input to the memory cell through a timing control line. Next, the write timing is generated based on a clock signal and the control signal. The write timing is enabled at the beginning of a cycle of the clock signal, and is disabled when the memory cell finishes the resistance state switching.Type: GrantFiled: January 8, 2012Date of Patent: January 7, 2014Assignee: Industrial Technology Research InstituteInventors: Pi-Feng Chiu, Shyh-Shyuan Sheu, Wen-Pin Lin, Chih-He Lin
-
Publication number: 20130121058Abstract: A circuit and a method for controlling the write timing of a non-volatile memory are provided. The method includes the following steps. First, a resistance state switching of at least one memory cell of the non-volatile memory executing a writing operation is monitored to output a control signal. The memory cell stores data states with different resistance states. A write timing is input to the memory cell through a timing control line. Next, the write timing is generated based on a clock signal and the control signal. The write timing is enabled at the beginning of a cycle of the clock signal, and is disabled when the memory cell finishes the resistance state switching.Type: ApplicationFiled: January 8, 2012Publication date: May 16, 2013Applicant: Industrial Technology Research InstituteInventors: Pi-Feng Chiu, Shyh-Shyuan Sheu, Wen-Pin Lin, Chih-He Lin
-
Publication number: 20130114325Abstract: A non-volatile random access memory (NV-RAM) and an operation method thereof are provided. The NV-RAM includes a latch unit, a switch, and a first to fourth non-volatile memory elements. First terminals of the first and the third non-volatile memory elements respectively couple to a first voltage and a second voltage. A second terminal of the first non-volatile memory element and a first terminal of the second non-volatile memory element are coupled to a first terminal of the latch unit. A second terminal of the third non-volatile memory element and a first terminal of the fourth non-volatile memory element are coupled to a second terminal of the latch unit. Second terminals of the second and the fourth non-volatile memory element are coupled to a first terminal of the switch. A second terminal of the switch is coupled to a third voltage.Type: ApplicationFiled: December 21, 2011Publication date: May 9, 2013Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chih-He Lin, Wen-Pin Lin, Pi-Feng Chiu, Shyh-Shyuan Sheu
-
Patent number: 8422295Abstract: A non-volatile random access memory (NV-RAM) and an operation method thereof are provided. The NV-RAM includes a latch unit, a switch, and a first to fourth non-volatile memory elements. First terminals of the first and the third non-volatile memory elements respectively couple to a first voltage and a second voltage. A second terminal of the first non-volatile memory element and a first terminal of the second non-volatile memory element are coupled to a first terminal of the latch unit. A second terminal of the third non-volatile memory element and a first terminal of the fourth non-volatile memory element are coupled to a second terminal of the latch unit. Second terminals of the second and the fourth non-volatile memory element are coupled to a first terminal of the switch. A second terminal of the switch is coupled to a third voltage.Type: GrantFiled: December 21, 2011Date of Patent: April 16, 2013Assignee: Industrial Technology Research InstituteInventors: Chih-He Lin, Wen-Pin Lin, Pi-Feng Chiu, Shyh-Shyuan Sheu
-
Patent number: 8392132Abstract: A process variation detection apparatus and a process variation detection method are provided. The process variation detection apparatus includes a process variation detector and a compensation signal generator. The process variation detector includes a first process variation detection component, a second process variation detection component and a current comparator. The channel of the first process variation detection component is a first conductive type, and the channel of the second process variation detection component is a second conductive type, wherein the above-mentioned first conductive type is different from the second conductive type. The current comparator is connected to the first process variation detection component and the second process variation detection component for comparing the current difference between the two components and outputting a current comparison result.Type: GrantFiled: August 5, 2010Date of Patent: March 5, 2013Assignee: Industrial Technology Research InstituteInventors: Ku-Feng Lin, Meng-Fan Chang, Shyh-Shyuan Sheu, Pei-Chia Chiang, Wen-Pin Lin, Chih-He Lin
-
Patent number: 8300449Abstract: A resistive random access memory (RRAM) and a verifying method thereof are provided. The RRAM comprises at least one resistive memory cell. The resistive memory cell comprises a resistive memory element and a transistor, wherein one terminal of the resistive memory element is coupled to a first terminal of the transistor. The verifying method comprises the following steps: Whether the resistive memory cell passes verification is determined. During a first time period and under the circumstance that the resistive memory cell fails to pass verification, a reference voltage is applied to the other terminal of the resistive memory element and a voltage pulse is applied to a second terminal of the transistor according to a voltage signal to write a reverse voltage to the resistive memory cell.Type: GrantFiled: November 29, 2010Date of Patent: October 30, 2012Assignee: Industrial Technology Research InstituteInventors: Chih-He Lin, Shyh-Shyuan Sheu, Wen-Pin Lin, Pei-Chia Chiang
-
Publication number: 20120075908Abstract: A resistive random access memory (RRAM) and a verifying method thereof are provided. The RRAM comprises at least one resistive memory cell. The resistive memory cell comprises a resistive memory element and a transistor, wherein one terminal of the resistive memory element is coupled to a first terminal of the transistor. The verifying method comprises the following steps: Whether the resistive memory cell passes verification is determined. During a first time period and under the circumstance that the resistive memory cell fails to pass verification, a reference voltage is applied to the other terminal of the resistive memory element and a voltage pulse is applied to a second terminal of the transistor according to a voltage signal to write a reverse voltage to the resistive memory cell.Type: ApplicationFiled: November 29, 2010Publication date: March 29, 2012Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chih-He Lin, Shyh-Shyuan Sheu, Wen-Pin Lin, Pei-Chia Chiang
-
Patent number: 8110416Abstract: Defects in components in ICs which may cause circuit failures during operation of the IC are often difficult to detect during and immediately after fabrication of the IC by DC test methods. A method of testing components to detect such defects using AC Impedance Spectroscopy is disclosed. Data may be analyzed using Nyquist plots and Bode plots. Nyquist plots of typical defect types are disclosed. Components may include MOS transistor gate structures, contacts, vias and metal interconnect lines. Components tested may be contained in integrated circuits or in test circuits. Integrated circuits containing components tested by AC Impedance Spectroscopy may be partially fabricated or deprocessed after fabrication.Type: GrantFiled: December 4, 2008Date of Patent: February 7, 2012Assignee: Texas Instruments IncorporatedInventors: Alfred J Griffin, He Lin
-
Publication number: 20110270555Abstract: A process variation detection apparatus and a process variation detection method are provided. The process variation detection apparatus includes a process variation detector and a compensation signal generator. The process variation detector includes a first process variation detection component, a second process variation detection component and a current comparator. The channel of the first process variation detection component is a first conductive type, and the channel of the second process variation detection component is a second conductive type, wherein the above-mentioned first conductive type is different from the second conductive type. The current comparator is connected to the first process variation detection component and the second process variation detection component for comparing the current difference between the two components and outputting a current comparison result.Type: ApplicationFiled: August 5, 2010Publication date: November 3, 2011Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Ku-Feng Lin, Meng-Fan Chang, Shyh-Shyuan Sheu, Pei-Chia Chiang, Wen-Pin Lin, Chih-He Lin