Abstract: A configurable logic block (CLB) and an operation method of the CLB are provided. The CLB includes memory units and a selecting circuit. The memory unit includes a first resistive non-volatile memory (RNVM) element and a second RNVM element. Top electrodes (TEs) of the first and second RNVM elements are coupled to an output terminal of the memory unit. Bottom electrodes (BEs) of the first and second RNVM elements are respectively coupled to a first bias terminal and a second bias terminal of the memory unit. The selecting circuit selects one of the memory units according to an input logic value and determines an output logic value of the CLB according to an output logic value of the selected memory unit.

Abstract: A self-learning regenerative braking control module is adapted for use with a vehicle, and includes a driving mode determining unit, an analyzing unit, and a regenerative braking determining unit. The driving mode determining unit determines a driving mode according to an accelerator signal, a brake signal, and a speed signal from the vehicle and outputs a coasting duration and coasting information associated with the driving mode to the analyzing unit for obtaining acceleration information. The regenerative braking determining unit obtains target regenerative braking data containing target vehicle speeds that vary with time based upon the acceleration information and regenerative braking reference data stored therein.

Abstract: An data search apparatus includes: a storage unit, storing a plurality of data; an input unit, inputting a data name, selecting a plurality of preference sets, and inputting a grading set by a user; a process unit, receiving the data name for searching for a plurality of candidate data from the data stored in a storage unit and generating a ranking result.

Abstract: A resistive random-access memory device includes a memory array, a read circuit, a write-back logic circuit and a write-back circuit. The read circuit reads the data stored in a selected memory cell and accordingly generates a first control signal. The write-back logic circuit generates a write-back control signal according to the first control signal and a second control signal. The write-back circuit performs a write-back operation on the selected memory cell according to the write-back control signal and a write-back voltage, so as to change a resistance state of the selected memory cell from a low resistance state to a high resistance state, and generates the second control signal according to the resistance state of the selected memory cell.

Abstract: A self-learning regenerative braking control module is adapted for use with a vehicle, and includes a driving mode determining unit, an analyzing unit, and a regenerative braking determining unit. The driving mode determining unit determines a driving mode according to an accelerator signal, a brake signal, and a speed signal from the vehicle and outputs a coasting duration and coasting information associated with the driving mode to the analyzing unit for obtaining acceleration information. The regenerative braking determining unit obtains target regenerative braking data containing target vehicle speeds that vary with time based upon the acceleration information and regenerative braking reference data stored therein.

Abstract: A logic gate including a first resistive non-volatile memory device and a second resistive non-volatile memory device is provided. When top electrodes of the first and the second resistive non-volatile memory devices are coupled to an output terminal of the logic gate, bottom electrodes of the first and the second resistive non-volatile memory devices are respectively coupled to a first input terminal and a second input terminal of the logic gate. When the bottom electrodes of the first and the second resistive non-volatile memory devices are coupled to the output terminal of the logic gate, the top electrodes of the first and the second resistive non-volatile memory devices are respectively coupled to the first input terminal and the second input terminal of the logic gate.

Abstract: A circuit and a method for controlling the write timing of a non-volatile memory are provided. The method includes the following steps. First, a resistance state switching of at least one memory cell of the non-volatile memory executing a writing operation is monitored to output a control signal. The memory cell stores data states with different resistance states. A write timing is input to the memory cell through a timing control line. Next, the write timing is generated based on a clock signal and the control signal. The write timing is enabled at the beginning of a cycle of the clock signal, and is disabled when the memory cell finishes the resistance state switching.

Abstract: A circuit and a method for controlling the write timing of a non-volatile memory are provided. The method includes the following steps. First, a resistance state switching of at least one memory cell of the non-volatile memory executing a writing operation is monitored to output a control signal. The memory cell stores data states with different resistance states. A write timing is input to the memory cell through a timing control line. Next, the write timing is generated based on a clock signal and the control signal. The write timing is enabled at the beginning of a cycle of the clock signal, and is disabled when the memory cell finishes the resistance state switching.

Abstract: A non-volatile random access memory (NV-RAM) and an operation method thereof are provided. The NV-RAM includes a latch unit, a switch, and a first to fourth non-volatile memory elements. First terminals of the first and the third non-volatile memory elements respectively couple to a first voltage and a second voltage. A second terminal of the first non-volatile memory element and a first terminal of the second non-volatile memory element are coupled to a first terminal of the latch unit. A second terminal of the third non-volatile memory element and a first terminal of the fourth non-volatile memory element are coupled to a second terminal of the latch unit. Second terminals of the second and the fourth non-volatile memory element are coupled to a first terminal of the switch. A second terminal of the switch is coupled to a third voltage.

Abstract: A non-volatile random access memory (NV-RAM) and an operation method thereof are provided. The NV-RAM includes a latch unit, a switch, and a first to fourth non-volatile memory elements. First terminals of the first and the third non-volatile memory elements respectively couple to a first voltage and a second voltage. A second terminal of the first non-volatile memory element and a first terminal of the second non-volatile memory element are coupled to a first terminal of the latch unit. A second terminal of the third non-volatile memory element and a first terminal of the fourth non-volatile memory element are coupled to a second terminal of the latch unit. Second terminals of the second and the fourth non-volatile memory element are coupled to a first terminal of the switch. A second terminal of the switch is coupled to a third voltage.

Abstract: A process variation detection apparatus and a process variation detection method are provided. The process variation detection apparatus includes a process variation detector and a compensation signal generator. The process variation detector includes a first process variation detection component, a second process variation detection component and a current comparator. The channel of the first process variation detection component is a first conductive type, and the channel of the second process variation detection component is a second conductive type, wherein the above-mentioned first conductive type is different from the second conductive type. The current comparator is connected to the first process variation detection component and the second process variation detection component for comparing the current difference between the two components and outputting a current comparison result.

Abstract: A resistive random access memory (RRAM) and a verifying method thereof are provided. The RRAM comprises at least one resistive memory cell. The resistive memory cell comprises a resistive memory element and a transistor, wherein one terminal of the resistive memory element is coupled to a first terminal of the transistor. The verifying method comprises the following steps: Whether the resistive memory cell passes verification is determined. During a first time period and under the circumstance that the resistive memory cell fails to pass verification, a reference voltage is applied to the other terminal of the resistive memory element and a voltage pulse is applied to a second terminal of the transistor according to a voltage signal to write a reverse voltage to the resistive memory cell.

Abstract: A resistive random access memory (RRAM) and a verifying method thereof are provided. The RRAM comprises at least one resistive memory cell. The resistive memory cell comprises a resistive memory element and a transistor, wherein one terminal of the resistive memory element is coupled to a first terminal of the transistor. The verifying method comprises the following steps: Whether the resistive memory cell passes verification is determined. During a first time period and under the circumstance that the resistive memory cell fails to pass verification, a reference voltage is applied to the other terminal of the resistive memory element and a voltage pulse is applied to a second terminal of the transistor according to a voltage signal to write a reverse voltage to the resistive memory cell.

Abstract: Defects in components in ICs which may cause circuit failures during operation of the IC are often difficult to detect during and immediately after fabrication of the IC by DC test methods. A method of testing components to detect such defects using AC Impedance Spectroscopy is disclosed. Data may be analyzed using Nyquist plots and Bode plots. Nyquist plots of typical defect types are disclosed. Components may include MOS transistor gate structures, contacts, vias and metal interconnect lines. Components tested may be contained in integrated circuits or in test circuits. Integrated circuits containing components tested by AC Impedance Spectroscopy may be partially fabricated or deprocessed after fabrication.

Abstract: A process variation detection apparatus and a process variation detection method are provided. The process variation detection apparatus includes a process variation detector and a compensation signal generator. The process variation detector includes a first process variation detection component, a second process variation detection component and a current comparator. The channel of the first process variation detection component is a first conductive type, and the channel of the second process variation detection component is a second conductive type, wherein the above-mentioned first conductive type is different from the second conductive type. The current comparator is connected to the first process variation detection component and the second process variation detection component for comparing the current difference between the two components and outputting a current comparison result.

Abstract: A voltage compensation circuit, a multi-level memory device with the same, and a voltage compensation method for reading the multi-level memory device are provided. When a memory cell is read, a reference voltage applied to the memory device is adjusted according to variation of characteristics of a drift resistance of a reference cell. The increased value of the reference voltage (i.e. a voltage difference) corresponds to a resistance variation caused by a drift condition. The drift compensation mechanism is adaptive to a compensation circuit of a read driver of the memory device, which can compensate variation of the voltage level when data is read from the memory cell. When the resistance drift occurs, a drift amount is calculated and is added to the reference voltage, in order to avoid the error in judgement caused by the resistance drift when the stored data is read out.

Abstract: A voltage compensation circuit, a multi-level memory device with the same, and a voltage compensation method for reading the multi-level memory device are provided. When a memory cell is read, a reference voltage applied to the memory device is adjusted according to variation of characteristics of a drift resistance of a reference cell. The increased value of the reference voltage (i.e. a voltage difference) corresponds to a resistance variation caused by a drift condition. The drift compensation mechanism is adaptive to a compensation circuit of a read driver of the memory device, which can compensate variation of the voltage level when data is read from the memory cell. When the resistance drift occurs, a drift amount is calculated and is added to the reference voltage, in order to avoid the error in judgement caused by the resistance drift when the stored data is read out.

Abstract: A biaxial folding lamp structure comprises a support unit, a first lighting unit and a second lighting unit, wherein the support unit has a first surface and a second surface; the first lighting unit is combined with the first surface via a first pivot; and the second lighting unit is combined with the second surface via a second pivot. With the first and second lighting units, the biaxial folding lamp structure can simultaneously provide lighting in two axial directions, thereby increasing an illuminated area. In addition, the first and second pivots allow the first and second lighting units to be folded up for storage.

Abstract: A board structure with an illumination light source comprises a board and a light source module, wherein the board has a first surface and an accommodating space, and the light source module is disposed in the accommodating space. By installing the light source module in the accommodating space and having light rays emitted from the light source module project upwards, an object placed on the board and adjacent to the accommodating space can be illuminated with the light rays focused and projected thereon.

Abstract: Defects in components in ICs which may cause circuit failures during operation of the IC are often difficult to detect during and immediately after fabrication of the IC by DC test methods. A method of testing components to detect such defects using AC Impedance Spectroscopy is disclosed. Data may be analyzed using Nyquist plots and Bode plots. Nyquist plots of typical defect types are disclosed. Components may include MOS transistor gate structures, contacts, vias and metal interconnect lines. Components tested may be contained in integrated circuits or in test circuits. Integrated circuits containing components tested by AC Impedance Spectroscopy may be partially fabricated or deprocessed after fabrication.