Patents by Inventor He-Zhou Wan

He-Zhou Wan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230290395
    Abstract: An integrated circuit includes integrated circuit includes a memory bank, a first group of word lines, a second group of word lines, an access circuit, a converter circuit and a decoder circuit. The first group of word lines is coupled to the memory bank. The second group of word lines is coupled to the memory bank, and arranged in order with the first group of word lines. The access circuit is configured to read the memory bank. The converter circuit is configured to control the access circuit at least based on a first control signal. The decoder circuit is configured to generate the first control signal at least according to a first bit and a second bit of an address signal. The first bit and the second bit indicates one group of the first group of word lines and the second group of word lines.
    Type: Application
    Filed: May 18, 2023
    Publication date: September 14, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY LIMITED
    Inventors: Xiu-Li YANG, He-Zhou WAN, Kuan CHENG, Ching-Wei WU
  • Patent number: 11651134
    Abstract: A method includes specifying a target memory macro, and determining failure rates of function-blocks in the target memory macro based on an amount of transistors and area distributions in a collection of base cells. The method also includes determining a safety level of the target memory macro, based upon a failure-mode analysis of the target memory macro, from a memory compiler, based on the determined failure rate.
    Type: Grant
    Filed: May 28, 2021
    Date of Patent: May 16, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC CHINA COMPANY, LIMITED
    Inventors: Ching-Wei Wu, Ming-En Bu, He-Zhou Wan, Hidehiro Fujiwara, Xiu-Li Yang
  • Publication number: 20230122135
    Abstract: A device is provided. The device includes multiple transistors, a first sense circuit, and a precharge circuit. The transistors are coupled to a tracking bit line and configured to generate a first tracking signal. The first sense circuit is configured to generate a first sense tracking signal in response to the first tracking signal. The precharge circuit is configured to generate, in response to a rising edge and a falling edge of the first sense tracking signal, a precharge signal for precharging data lines.
    Type: Application
    Filed: December 20, 2022
    Publication date: April 20, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC Nanjing Company Limited, TSMC China Company Limited
    Inventors: Xiu-Li YANG, He-Zhou WAN, Lu-Ping KONG, Wei-Yang JIANG
  • Publication number: 20230114646
    Abstract: A circuit includes a power management circuit configured to receive at least a first or a second control signal, and to supply at least a first, second or a third supply voltage. The first control signal has a first voltage swing. The second control signal has a second voltage swing. The power management circuit includes a first level shifter circuit configured to generate a first level shifted signal in response to the first control signal, and a first header circuit coupled to at least the first level shifter circuit, a first voltage supply and a second voltage supply. The first header circuit is configured to supply the first supply voltage of the first voltage supply to the first node in response to the first control signal, and to supply the second supply voltage of the second voltage supply to the second node in response to the first level shifted signal.
    Type: Application
    Filed: December 15, 2022
    Publication date: April 13, 2023
    Inventors: Xiu-Li YANG, Ching-Wei WU, He-Zhou WAN, Ming-En BU
  • Publication number: 20230105594
    Abstract: A device includes a first memory bank and a second memory bank. The first memory bank is configured to operate according to a write data signal and a first global write signal associated with a first clock signal. The second memory bank is configured to operate according to the write data signal and a second global write signal associated with a second clock signal. One of the first clock signal and the second clock signal is in oscillation when another one of the first clock signal and the second clock signal is in suspension.
    Type: Application
    Filed: December 2, 2022
    Publication date: April 6, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY LIMITED
    Inventors: Xiu-Li YANG, Kuan CHENG, He-Zhou WAN, Wei-Yang JIANG
  • Publication number: 20230105283
    Abstract: A device includes a first virtual power line coupled to a power supply through a first group of transistor switches, and a second virtual power line configured to receive the power supply through a second group of transistor switches. The device also includes a delay circuit coupled between the gate terminals of the first group of transistor switches and the gate terminals in the second group of transistor switches. The device further includes a wakeup detector and a plurality of main input-output (MIO) controllers. The wakeup detector is configured to generate a trigger signal after receiving a signal from the output of the delay circuit. The plurality of MIO controllers is coupled to the power supply through a group of wakeup switches and through a group of function switches. The gate terminals in the group of wakeup switches are configured to receive the trigger signal.
    Type: Application
    Filed: December 9, 2022
    Publication date: April 6, 2023
    Inventors: He-Zhou WAN, XiuLi YANG, Ming-En BU, Mengxiang XU, Zong-Liang CAO
  • Publication number: 20230049698
    Abstract: A memory device includes a first transistor, a second transistor and a third transistor. The first transistor is coupled to a first word line at a first node. The second transistor is coupled to a second word line different from the first word line at a second node. A control terminal of the first transistor is coupled to a control terminal of the second transistor. The third transistor is coupled between a ground and a third node which is coupled to each of the first node and the second node. In a layout view, each of the first transistor and the second transistor has a first length along a direction. The first transistor, the third transistor and second transistor are arranged in order along the direction. A method is also disclosed herein.
    Type: Application
    Filed: October 26, 2022
    Publication date: February 16, 2023
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC Nanjing Company Limited, TSMC China Company Limited
    Inventors: He-Zhou WAN, Xiu-Li YANG, Mu-Yang YE, Yan-Bo SONG
  • Patent number: 11557336
    Abstract: A device is disclosed. The device includes a first tracking control line, a first tracking circuit, a first sense circuit, and a precharge circuit. The first tracking control line is configured to transmit a first tracking control signal. The first tracking circuit is configured to generate, in response to the first tracking control signal, a first tracking signal associated with first tracking cells in a memory array. The first sense circuit is configured to receive the first tracking signal, and is configured to generate a first sense tracking signal in response to the first tracking signal. The precharge circuit is configured to generate, in response to a rising edge of the first sense tracking signal and a falling edge of a read enable delayed signal, a precharge signal for precharging data lines associated with memory cell in the memory array. A method is also disclosed herein.
    Type: Grant
    Filed: November 30, 2020
    Date of Patent: January 17, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITED
    Inventors: Xiu-Li Yang, He-Zhou Wan, Lu-Ping Kong, Wei-Yang Jiang
  • Patent number: 11545191
    Abstract: A circuit includes a power management circuit and a memory circuit. The power management circuit is configured to receive a first control signal and a second control signal, and to supply a first supply voltage, a second supply voltage and a third supply voltage. The first control signal has a first voltage swing, and the second control signal has a second voltage swing different from the first voltage swing. The first control signal causes the power management circuit to enter a power management mode having a first state and a second state. The memory circuit is coupled to the power management circuit, and is in the first state or the second state in response to at least the first supply voltage supplied by the power management circuit.
    Type: Grant
    Filed: February 3, 2021
    Date of Patent: January 3, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY. LIMITED
    Inventors: Xiu-Li Yang, Ching-Wei Wu, He-Zhou Wan, Ming-En Bu
  • Patent number: 11545192
    Abstract: A device includes a first virtual power line, a second virtual power line, a first delay circuit, and a first wakeup detector. The first virtual power line and the second virtual power line are coupled to a power supply correspondingly through a first group of transistor switches and a second group of transistor switches. The first delay circuit is coupled between gate terminals of the first group of transistor switches and gate terminals in the second group of transistor switches. The first wakeup detector is configured to generate a first trigger signal after receiving a signal from the first delay circuit.
    Type: Grant
    Filed: February 25, 2021
    Date of Patent: January 3, 2023
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMITED
    Inventors: He-Zhou Wan, XiuLi Yang, Ming-En Bu, Mengxiang Xu, Zong-Liang Cao
  • Patent number: 11521662
    Abstract: A device includes memory banks, a first pair of write data wirings, a second pair of write data wirings and a global write circuit. The first pair of write data wirings is connected to a first group among the memory banks. The second pair of write data wirings is connected to a second group among the memory banks. In response to a first clock signal, the global write circuit generates a first global write signal and a first complement global write signal transmitted to the first group among the memory banks through the first pair of write data wirings. In response to a second clock signal, the global write circuit generates a second global write signal and a second complement global write signal transmitted to the second group among the memory banks through the second pair of write data wirings.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: December 6, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY LIMITED
    Inventors: Xiu-Li Yang, Kuan Cheng, He-Zhou Wan, Wei-Yang Jiang
  • Patent number: 11514974
    Abstract: A memory device includes a word line driver. The word line driver is coupled through word lines to an array of bit cells. The word line driver includes a first driving circuit, a second driving circuit and a modulating circuit. The first driving circuit and the second driving circuit are configured to select a word line. The modulating circuit is coupled through the selected word line to the first driving circuit and the second driving circuit, and is configured to modulate at least one signal transmitted through the selected word line. The first driving circuit and the second driving circuit are further configured to charge the selected word line to generate a first voltage signal and a second voltage signal at two positions of the selected word line. The first voltage signal is substantially the same as the second voltage signal. A method is also disclosed herein.
    Type: Grant
    Filed: March 22, 2021
    Date of Patent: November 29, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITED
    Inventors: He-Zhou Wan, Xiu-Li Yang, Mu-Yang Ye, Yan-Bo Song
  • Publication number: 20220375512
    Abstract: A circuit includes a plurality of registers, each register including SRAM cells, a read port configured to receive a read address, a write port configured to receive a write address, a selection circuit, a latch circuit, and a decoder coupled in series between the read and write ports and the plurality of registers, and a control circuit. Responsive to a clock signal and read and write enable signals, the control circuit causes the selection circuit, the latch circuit, and the decoder to select a first register of the plurality of registers in a read operation based on the read address, and select a second register of the plurality of registers in a write operation based on the write address.
    Type: Application
    Filed: August 8, 2022
    Publication date: November 24, 2022
    Inventors: XiuLi YANG, Ching-Wei WU, He-Zhou WAN, Kuan CHENG, Luping KONG
  • Publication number: 20220366950
    Abstract: A memory circuit includes a NAND logic gate configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The memory circuit further includes a first N-type transistor coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The memory circuit further includes a second N-type transistor coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The memory circuit further includes a first latch coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.
    Type: Application
    Filed: July 29, 2022
    Publication date: November 17, 2022
    Inventors: Yi-Tzu CHEN, Ching-Wei WU, Hau-Tai SHIEH, Hung-Jen LIAO, Fu-An WU, He-Zhou WAN, XiuLi YANG
  • Publication number: 20220367484
    Abstract: A memory device includes a first memory array, a first isolation cell abutting a first side of the first memory array, a first edge cell array abutting a second side, opposite to the first side, of the first memory array, a second memory array arranged at a first side, opposite to the first memory array, of the first isolation cell, a second edge cell array, and multiple first word lines passing through the first edge cell array, the first memory array and being terminated at the first isolation cell. A first width of the first isolation cell is different from a second width of the first edge cell array. The second memory array is sandwiched between the second edge cell array and the first isolation cell.
    Type: Application
    Filed: July 29, 2022
    Publication date: November 17, 2022
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY LIMITED
    Inventors: Xiu-Li YANG, He-Zhou WAN, Yan-Bo SONG
  • Publication number: 20220335988
    Abstract: A memory device includes a local input/output circuit and a main input/output circuit. The local input/output circuit is configured to generate a first local write signal based on a first global write signal and a second global write signal, and configured to transmit the first local write signal to a plurality of first bit lines. The main input/output circuit include a first latch and logic elements. The first latch is configured to generate a first bit write mask signal based on a clock signal. The logic elements are configured to generate the first global write signal and the second global write signal based on the clock signal and the first bit write mask signal.
    Type: Application
    Filed: June 29, 2022
    Publication date: October 20, 2022
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC Nanjing Company Limited, TSMC China Company Limited
    Inventors: He-Zhou WAN, Xiu-Li YANG, Pei-Le LI, Ching-Wei WU
  • Publication number: 20220335992
    Abstract: A device includes a memory array, bit line pairs, word lines, a modulation circuit and a control signal generator. The memory array has bit cells arranged in rows and columns. Each bit line pair is connected to a respective column of bit cells. Each word line is connected to a respective row of bit cells. The modulation circuit is coupled with at least one bit line pair. The control signal generator is coupled with the modulation circuit. The control signal generator includes a tracking wiring with a tracking length positively correlated with a depth distance of the word lines. The control signal generator is configured to produce a control signal, switching to a first voltage level for a first time duration in reference with the tracking length, for controlling the modulation circuit. A method of controlling aforesaid device is also disclosed.
    Type: Application
    Filed: July 5, 2022
    Publication date: October 20, 2022
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC NANJING COMPANY LIMITED, TSMC CHINA COMPANY LIMITED
    Inventors: Xiu-Li YANG, He-Zhou WAN, Mu-Yang YE, Lu-Ping KONG, Ming-Hung CHANG
  • Patent number: 11468929
    Abstract: A memory circuit includes a NAND logic gate, a first N-type transistor, a second N-type transistor, a first inverter and a first latch. The NAND logic gate is configured to receive a first bit line signal and a second bit line signal, and to generate a first signal. The first N-type transistor is coupled to the NAND logic gate, and configured to receive a first pre-charge signal. The second N-type transistor is coupled to the first N-type transistor and a reference voltage supply, and configured to receive a first clock signal. The first inverter is coupled to the NAND logic gate, and configured to output a data signal inverted from the first signal. The first latch is coupled to the NAND logic gate, and configured to latch the first signal in response to at least the first clock signal or the first pre-charge signal.
    Type: Grant
    Filed: April 20, 2021
    Date of Patent: October 11, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMITED
    Inventors: Yi-Tzu Chen, Ching-Wei Wu, Hau-Tai Shieh, Hung-Jen Liao, Fu-An Wu, He-Zhou Wan, XiuLi Yang
  • Patent number: 11462551
    Abstract: A memory device includes a first isolation cell, a first memory array of a first memory segment, a second memory array of a second memory segment, a first decoder cell of the first memory segment and a second decoder cell of the second memory segment. The first isolation cell extends in a first direction. The first memory array of the first memory segment abuts a first boundary of the first isolation cell in a second direction different from the first direction. The second memory array of the second memory segment abuts a second boundary, opposite to the first boundary, of the first isolation cell in the second direction. The first decoder cell of the first memory segment and the second decoder cell of the second memory segment are arranged on opposite sides of the first isolation cell.
    Type: Grant
    Filed: April 8, 2021
    Date of Patent: October 4, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY LIMITED
    Inventors: Xiu-Li Yang, He-Zhou Wan, Yan-Bo Song
  • Patent number: 11450367
    Abstract: A circuit includes a selection circuit configured to receive a first address from a first port and a second address from a second port, a first latch circuit coupled to the selection circuit and configured to output each of the first address and the second address received from the selection circuit, a decoder, and a control circuit. The control circuit is configured to generate a plurality of signals configured to cause the decoder to decode each of the first address and the second address.
    Type: Grant
    Filed: February 23, 2021
    Date of Patent: September 20, 2022
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., TSMC CHINA COMPANY, LIMITED, TSMC NANJING COMPANY, LIMITED
    Inventors: XiuLi Yang, Ching-Wei Wu, He-Zhou Wan, Kuan Cheng, Luping Kong