Abstract: A clock divider for a DLL circuit reduces power consumption by reducing the number of times of performing phase comparison in the DLL circuit when a synchronous memory device is in a power-down mode. The clock divider includes M dividers and a power-down controller for receiving an output signal of the (M?1)-th divider and an output signal of the M-th divider and selectively outputting the output signals. Each divider divides the clock signal frequency inputted to the divider by ½. The output signal frequency of the power-down controller is obtained by dividing the frequency of the clock signal inputted to the first divider into ½M or ½(M-1) depending on the logic level of a control signal, which is indicative of the power down mode of the memory device.

Abstract: A clock divider for a DLL circuit reduces power consumption by reducing the number of times of performing phase comparison in the DLL circuit when a synchronous memory device is in a power-down mode. The clock divider includes M dividers and a power-down controller for receiving an output signal of the (M?1)-th divider and an output signal of the M-th divider and selectively outputting the output signals. Each divider divides the clock signal frequency inputted to the divider by ½. The output signal frequency of the power-down controller is obtained by dividing the frequency of the clock signal inputted to the first divider into ½M or ½(M?1) depending on the logic level of a control signal, which is indicative of the power down mode of the memory device.

Abstract: A register controlled delay locked loop (DLL) includes a clock divider, a shift controller, a delay unit and a delay model to synchronize an external clock signal with an internal clock. The register controlled DLL further includes a reset signal generator to generate a reset signal used to initialize the delay locked loop (DLL), a phase comparator to initialize a phase comparison signal in which the phase of a feedback clock signal delayed by a reference clock signal and the delay model is compared and outputted into a predetermined signal by using a comparison enable signal having an inverse phase to that of the reset signal, and a shift register to block an electric current running on a first latch of a plurality of latches with the reset signal during the initialization.

Abstract: A divider of a DLL(delay locked loop) measures tAC for various periods due to variation of process, temperature and a supply voltage and provides a divided clock having an optimum tAC. The clock divider includes a clock dividing unit, a test mode clock providing unit and a normal mode clock providing unit. The clock dividing unit receives a source clock of the DLL to generate a plurality of divided clocks, each having a period different from each other. The test mode clock providing unit selectively outputs the plurality of the divided clocks in a test mode in response to a test mode signal and a test mode period selecting signal. And, the normal mode clock providing unit outputs selected one of the plurality of the divided clocks in a normal mode in response to the test mode signal.

Abstract: A delay locked loop (DLL) in a semiconductor device, includes an clock buffer receiving an external clock signal and an inverted clock signal and outputting first and second internal clock signals to be used in the DLL circuit; and a variable clock divider receiving the second internal signal from the clock buffer and variably dividing the second internal clock signal to have a predetermined pulse width according to a control signal based on a column address strobe (CAS) latency, which is set according to a frequency of the external clock signal, wherein the control signal is initially set to have a first logic level and is enabled to a second logic level when the CAS latency corresponds to a high frequency.

Abstract: A delayed locked loop in a semiconductor memory device includes a read enable signal generating block for generating a read enable signal, wherein the read enable signal is enabled based on the application of a read command, and is disabled when all data is read out and outputted; a first internal clock controlling block for intermitting the output of a first internal clock through the use of the read enable signal; a second internal clock controlling block for intermitting the output of a second internal clock through the use of the read enable signal; a DLL clock generating block for receiving the first and second internal clocks to thereby generate first and second DLL clocks.

Abstract: A divider of a DLL(delay locked loop) measures tAC for various periods due to variation of process, temperature and a supply voltage and provides a divided clock having an optimum tAC. The clock divider includes a clock dividing unit, a test mode clock providing unit and a normal mode clock providing unit. The clock dividing unit receives a source clock of the DLL to generate a plurality of divided clocks, each having a period different from each other. The test mode clock providing unit selectively outputs the plurality of the divided clocks in a test mode in response to a test mode signal and a test mode period selecting signal. And, the normal mode clock providing unit outputs selected one of the plurality of the divided clocks in a normal mode in response to the test mode signal.

Abstract: A clock divider for a DLL circuit can reduce the power consumption by reducing the number of times of phase comparison in the DLL circuit when a synchronous memory device is in a power-down mode. The clock divider includes M dividers connected in series, and a power-down controller for receiving an output signal of the (M−1)-th divider and an output signal of the M-th divider and selectively outputting the output signals. The respective dividers divide a frequency of a clock signal inputted to the respective dividers into ½, and the output signal of the power-down controller has a frequency obtained by dividing the frequency of the clock signal inputted to the first divider into ½M or ½(M−1) in accordance with a logic level of a control signal.

Abstract: A delay locked loop (DLL) in a semiconductor device, includes an clock buffer receiving an external clock signal and an inverted clock signal and outputting first and second internal clock signals to be used in the DLL circuit; and a variable clock divider receiving the second internal signal from the clock buffer and variably dividing the second internal clock signal to have a predetermined pulse width according to a control signal based on a column address strobe (CAS) latency, which is set according to a frequency of the external clock signal, wherein the control signal is initially set to have a first logic level and is enabled to a second logic level when the CAS latency corresponds to a high frequency.

Abstract: A delay locked loop (DLL) usable in a semiconductor memory device and capable of reducing current consumption by operating the DLL loop when the semiconductor device is only at an operation mode, is provided.

Abstract: A register controlled delay locked loop (DLL) includes a clock divider, a shift controller, a delay unit and a delay model to synchronize an external clock signal with an internal clock. The register controlled DLL further includes a reset signal generator to generate a reset signal used to initialize the delay locked loop (DLL), a phase comparator to initialize a phase comparison signal in which the phase of a feedback clock signal delayed by a reference clock signal and the delay model is compared and outputted into a predetermined signal by using a comparison enable signal having an inverse phase to that of the reset signal, and a shift register to block an electric current running on a first latch of a plurality of latches with the reset signal during the initialization.

Abstract: A delay locked loop (DLL) usable in a semiconductor memory device and capable of reducing current consumption by operating the DLL loop when the semiconductor device is only at an operation mode, is provided.

Abstract: A delay locked loop is disclosed which is less responsive to noise so as to improve an AC parameter tAC. The delay locked loop generally includes: a phase detector, a shift register, and a noise determining circuit which is enabled when the delay locked loop is locked for controlling driving of the shift register by determining whether a phase comparison signal from the phase detector is produced by noise. The noise determining circuit drives the shift register when the phase comparison signal has information for driving the shift register at least three times sequentially.

Abstract: A delay locked loop (DLL) for use in a synchronous memory device includes: a first shift controller for generating a first shift-right signal in response to a first comparison signal; a first shift register for performing only a shift-right operation in response to the first shift-right signal; a first delay line unit for controlling each delay amount of internal signals in response to an output of the first shift register, wherein the first delay line unit includes a plurality of delay lines, each delay line having a first unit delay; a second shift controller for generating a second shift-right signal and a shift-left signal in response to a second comparison signal; a second shift register for performing a shift-right operation and a shift-left operation in response to the second shift-right signal and the shift-left signal, respectively; and a second delay line unit for controlling each delay amount of output signals of the first delay line means, wherein the second delay line unit includes a plurality of

Abstract: A delay locked loop is disclosed which is less responsive to noise so as to improve an AC parameter tAC. The delay locked loop generally includes: a phase detector, a shift register, and a noise determining circuit which is enabled when the delay locked loop is locked for controlling driving of the shift register by determining whether a phase comparison signal from the phase detector is produced by noise. The noise determining circuit drives the shift register when the phase comparison signal has information for driving the shift register at least three times sequentially.

Abstract: A delay locked loop (DLL) for use in a synchronous memory device includes: a first shift controller for generating a first shift-right signal in response to a first comparison signal; a first shift register for performing only a shift-right operation in response to the first shift-right signal; a first delay line unit for controlling each delay amount of internal signals in response to an output of the first shift register, wherein the first delay line unit includes a plurality of delay lines, each delay line having a first unit delay; a second shift controller for generating a second shift-right signal and a shift-left signal in response to a second comparison signal; a second shift register for performing a shift-right operation and a shift-left operation in response to the second shift-right signal and the shift-left signal, respectively; and a second delay line unit for controlling each delay amount of output signals of the first delay line means, wherein the second delay line unit includes a plurality of