Patents by Inventor Heap Hoe Kuan

Heap Hoe Kuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10217873
    Abstract: A semiconductor device has a first semiconductor die including an active region formed on a surface of the first semiconductor die. The active region of the first semiconductor die can include a sensor. An encapsulant is deposited over the first semiconductor die. A conductive layer is formed over the encapsulant and first semiconductor die. An insulating layer can be formed over the first semiconductor die. An opening is formed in the insulating layer over the active region. A transmissive layer is formed over the first semiconductor die including the active region. The transmissive layer includes an optical dielectric material or an optical transparent or translucent material. The active region is responsive to an external stimulus passing through the transmissive layer. A plurality of bumps is formed through the encapsulant and electrically connected to the conductive layer. A second semiconductor die is disposed adjacent to the first semiconductor die.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: February 26, 2019
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Joon Han, Il Kwon Shim, Heap Hoe Kuan
  • Patent number: 9847253
    Abstract: A semiconductor package-on-package (PoP) device includes a first die incorporating a through-hole via (THV) disposed along a peripheral surface of the first die. The first die is disposed over a substrate or leadframe structure. A first semiconductor package is electrically connected to the THV of the first die, or electrically connected to the substrate or leadframe structure. An encapsulant is formed over a portion of the first die and the first semiconductor package.
    Type: Grant
    Filed: April 9, 2010
    Date of Patent: December 19, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Tai Do, Heap Hoe Kuan, Seng Guan Chow
  • Publication number: 20170110599
    Abstract: A semiconductor device has a first semiconductor die including an active region formed on a surface of the first semiconductor die. The active region of the first semiconductor die can include a sensor. An encapsulant is deposited over the first semiconductor die. A conductive layer is formed over the encapsulant and first semiconductor die. An insulating layer can be formed over the first semiconductor die. An opening is formed in the insulating layer over the active region. A transmissive layer is formed over the first semiconductor die including the active region. The transmissive layer includes an optical dielectric material or an optical transparent or translucent material. The active region is responsive to an external stimulus passing through the transmissive layer. A plurality of bumps is formed through the encapsulant and electrically connected to the conductive layer. A second semiconductor die is disposed adjacent to the first semiconductor die.
    Type: Application
    Filed: December 29, 2016
    Publication date: April 20, 2017
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Joon Han, Il Kwon Shim, Heap Hoe Kuan
  • Patent number: 9564413
    Abstract: A semiconductor device has a first semiconductor die including an active region formed on a surface of the first semiconductor die. The active region of the first semiconductor die can include a sensor. An encapsulant is deposited over the first semiconductor die. A conductive layer is formed over the encapsulant and first semiconductor die. An insulating layer can be formed over the first semiconductor die. An opening is formed in the insulating layer over the active region. A transmissive layer is formed over the first semiconductor die including the active region. The transmissive layer includes an optical dielectric material or an optical transparent or translucent material. The active region is responsive to an external stimulus passing through the transmissive layer. A plurality of bumps is formed through the encapsulant and electrically connected to the conductive layer. A second semiconductor die is disposed adjacent to the first semiconductor die.
    Type: Grant
    Filed: July 10, 2012
    Date of Patent: February 7, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Joon Han, Il Kwon Shim, Heap Hoe Kuan
  • Patent number: 9553162
    Abstract: A semiconductor device has a semiconductor die and an encapsulant deposited over the semiconductor die. A conductive layer can be formed over the encapsulant and the semiconductor die. A transmissive layer can be formed over the semiconductor die. An interconnect structure can be formed through the encapsulant and electrically connected to the conductive layer, whereby the interconnect structure is formed off to only one side of the semiconductor die.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: January 24, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Thomas J. Strothmann, Steve Anderson, Byung Joon Han, Il Kwon Shim, Heap Hoe Kuan
  • Patent number: 9524955
    Abstract: A semiconductor device is made by forming a conductive layer over a first sacrificial carrier. A solder bump is formed over the conductive layer. A no-flow underfill material is deposited over the first carrier, conductive layer, and solder bump. A semiconductor die or component is compressed into the no-flow underfill material to electrically contact the conductive layer. A surface of the no-flow underfill material and first solder bump is planarized. A first interconnect structure is formed over a first surface of the no-flow underfill material. The first interconnect structure is electrically connected to the solder bump. A second sacrificial carrier is mounted over the first interconnect structure. A second interconnect structure is formed over a second side of the no-flow underfill material. The second interconnect structure is electrically connected to the first solder bump. The semiconductor devices can be stacked and electrically connected through the solder bump.
    Type: Grant
    Filed: March 19, 2012
    Date of Patent: December 20, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Rui Huang, Heap Hoe Kuan, Yaojian Lin, Seng Guan Chow
  • Patent number: 9524938
    Abstract: A semiconductor device includes a first die having top, bottom, and peripheral surfaces. A bond pad is formed over the top surface. An organic material is connected to the first die and disposed around the peripheral surface. A via hole is formed in the organic material. A metal trace connects the via hole to the bond pad. A conductive material is deposited in the via hole. A redistribution layer (RDL) has an interconnection pad disposed over the top surface of the first die.
    Type: Grant
    Filed: March 18, 2013
    Date of Patent: December 20, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Tai Do, Heap Hoe Kuan, Seng Guan Chow
  • Patent number: 9515016
    Abstract: A semiconductor package is made using a prefabricated post carrier including a base plate and plurality of conductive posts. A film encapsulant is disposed over the base plate of the post carrier and around the conductive posts. A semiconductor die is mounted to a temporary carrier. The post carrier and temporary carrier are pressed together to embed the semiconductor die in the film encapsulant. The semiconductor die is disposed between the conductive posts in the film encapsulant. The temporary carrier and base plate of the post carrier are removed. A first circuit build-up layer is formed over a first side of the film encapsulant. The first circuit build-up layer is electrically connected to the conductive posts. A second circuit build-up layer is formed over a second side of the film encapsulant opposite the first side. The second circuit build-up layer is electrically connected to the conductive posts.
    Type: Grant
    Filed: November 20, 2012
    Date of Patent: December 6, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Rui Huang, Il Kwon Shim, Seng Guan Chow, Heap Hoe Kuan
  • Patent number: 9406647
    Abstract: A semiconductor device is manufactured by, first, providing a wafer, designated with a saw street guide, and having a bond pad formed on an active surface of the wafer. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A redistribution layer is patterned over a portion of the organic material. An under bump metallization (UBM) is deposited over the organic material in electrical communication, through the redistribution layer, with the bond pad.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: August 2, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Tai Do, Heap Hoe Kuan
  • Patent number: 9299648
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a package substrate having a component side and a system side; depositing a solder resist layer on the component side of the package substrate; patterning groups of access openings and a die mount opening in the solder resist layer; attaching an integrated circuit die in the die mount opening; forming conductive contacts in the access openings; and attaching system interconnects to the system side of the package substrate including controlling a coplanarity of the system interconnects by the solder resist layer.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: March 29, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Il Kwon Shim, Seng Guan Chow, Heap Hoe Kuan
  • Patent number: 9293350
    Abstract: A method of manufacturing a semiconductor package system includes: providing a first substrate; providing a second substrate having a cavity, the second substrate being attached to the first substrate; connecting the first substrate to the second substrate using an interconnect, the interconnect being in the cavity; and attaching a semiconductor device to the first substrate or the second substrate.
    Type: Grant
    Filed: October 28, 2008
    Date of Patent: March 22, 2016
    Assignee: STATS ChipPAC Ltd.
    Inventors: Seng Guan Chow, Rui Huang, Heap Hoe Kuan
  • Patent number: 9275877
    Abstract: A semiconductor device has a first insulating layer formed over a carrier. A first conductive layer is formed over the first insulating layer. A second insulating layer is formed over the first conductive layer. Vias are formed through the second insulating layer. A second conductive layer is formed over the second insulating layer and extends into the vias. A semiconductor die is mounted to the second conductive layer. A bond wire is formed between a contact pad on the semiconductor die and the second conductive layer. The second conductive layer extends to a mounting site of the semiconductor die to minimize the bond wire span. An encapsulant is deposited over the semiconductor die. A portion of the first insulating layer is removed to expose the second conductive layer. A portion of the first conductive layer is removed to electrically isolate remaining portions of the first conductive layer.
    Type: Grant
    Filed: September 20, 2011
    Date of Patent: March 1, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Yaojian Lin, Rui Huang, Heap Hoe Kuan, Seng Guan Chow
  • Patent number: 9257356
    Abstract: A semiconductor device has a conductive layer formed on a substrate. The conductive layer has a first portion constituting contact pads and a second portion constituting an integrated passive device such as an inductor. A spacer is formed on the substrate around the second portion of the conductive layer. The spacer can be insulating material or conductive material for shielding. A semiconductor die is mounted to the spacer. An electrical connection is formed between contact pads on the semiconductor die and the contact pads on the substrate. An encapsulant is formed around the semiconductor die, electrical connections, spacer, and conductive layer. The substrate is removed to expose the conductive layer. An interconnect structure is formed on the backside of the substrate. The interconnect structure is electrically connected to the conductive layer. The semiconductor device can be integrated into a package.
    Type: Grant
    Filed: December 10, 2008
    Date of Patent: February 9, 2016
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Rui Huang, Heap Hoe Kuan, Yaojian Lin, Seng Guan Chow
  • Patent number: 9177848
    Abstract: A semiconductor wafer contains a plurality of die with contact pads disposed on a first surface of each die. Metal vias are formed in trenches in the saw street guides and are surrounded by organic material. Traces connect the contact pads and metal vias. The metal vias can be half-circle vias or full-circle vias. The metal vias are surrounded by organic material. Redistribution layers (RDL) are formed on a second surface of the die opposite the first surface. The RDL and through-hole vias (THV) provide expanded interconnect flexibility to adjacent die. Repassivation layers are formed between the RDL on the second surface of the die for electrical isolation. The die are stackable and can be placed in a semiconductor package with other die. The RDL provide electrical interconnect to the adjacent die. Bond wires and solder bumps also provide electrical connection to the semiconductor die.
    Type: Grant
    Filed: July 6, 2012
    Date of Patent: November 3, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Byung Tai Do, Heap Hoe Kuan, Linda Pei Ee Chua
  • Patent number: 9123733
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a sacrificial carrier assembly having a stack interconnector thereover; mounting an integrated circuit having a connector over the sacrificial carrier assembly with the connector over the stack interconnector; dispensing an underfill material between the sacrificial carrier assembly and the integrated circuit with the underfill material substantially free of a void; encapsulating the integrated circuit over the sacrificial carrier assembly and the underfill material; exposing the stack interconnector by removing the sacrificial carrier assembly; and forming a base array over the underfill material and the stack interconnector.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: September 1, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Rui Huang, Heap Hoe Kuan, Yaojian Lin, Seng Guan Chow
  • Patent number: 9099455
    Abstract: A semiconductor package includes a post carrier having a base plate and plurality of conductive posts. A photosensitive encapsulant is deposited over the base plate of the post carrier and around the conductive posts. The photosensitive encapsulant is etched to expose a portion of the base plate of the post carrier. A semiconductor die is mounted to the base plate of the post carrier within the etched portions of the photosensitive encapsulant. A second encapsulant is deposited over the semiconductor die. A first circuit build-up layer is formed over the second encapsulant. The first circuit build-up layer is electrically connected to the conductive posts. The base plate of the post carrier is removed and a second circuit build-up layer is formed over the semiconductor die and the photosensitive encapsulant opposite the first circuit build-up layer. The second circuit build-up layer is electrically connected to the conductive posts.
    Type: Grant
    Filed: November 21, 2012
    Date of Patent: August 4, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Seng Guan Chow, Il Kwon Shim, Heap Hoe Kuan, Rui Huang
  • Patent number: 9064876
    Abstract: A semiconductor device has a substrate with a cavity formed through first and second surfaces of the substrate. A conductive TSV is formed through a first semiconductor die, which is mounted in the cavity. The first semiconductor die may extend above the cavity. An encapsulant is deposited over the substrate and a first surface of the first semiconductor die. A portion of the encapsulant is removed from the first surface of the first semiconductor die to expose the conductive TSV. A second semiconductor die is mounted to the first surface of the first semiconductor die. The second semiconductor die is electrically connected to the conductive TSV. An interposer is disposed between the first semiconductor die and second semiconductor die. A third semiconductor die is mounted over a second surface of the first semiconductor die. A heat sink is formed over a surface of the third semiconductor die.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: June 23, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Heap Hoe Kuan, Dioscoro A. Merilo
  • Patent number: 9059186
    Abstract: An embedded semiconductor die package is made by mounting a frame carrier to a temporary carrier with an adhesive. The frame carrier includes die mounting sites each including a leadframe interconnect structure around a cavity. A semiconductor die is disposed in each cavity. An encapsulant is deposited in the cavity over the die. A package interconnect structure is formed over the leadframe interconnect structure and encapsulant. The package interconnect structure and leadframe interconnect structure are electrically connected to the die. The frame carrier is singulated into individual embedded die packages. The semiconductor die can be vertically stacked or placed side-by-side within the cavity. The embedded die packages can be stacked and electrically interconnected through the leadframe interconnect structure. A semiconductor device can be mounted to the embedded die package and electrically connected to the die through the leadframe interconnect structure.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: June 16, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Il Kwon Shim, Seng Guan Chow, Heap Hoe Kuan
  • Patent number: 9048197
    Abstract: An integrated circuit package system that includes: providing a substrate with a protective coating; attaching a labeling film to a support member in a separate process; joining the protective coating and the labeling film; and dicing the substrate, the protective coating, and the labeling film to form the integrated circuit package system.
    Type: Grant
    Filed: February 19, 2010
    Date of Patent: June 2, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Byung Tai Do, Heap Hoe Kuan
  • Patent number: 9030006
    Abstract: An integrated circuit package system includes: providing an integrated circuit substrate; forming an internal stacking module coupled to the integrated circuit substrate including: forming a flexible substrate, coupling a stacking module integrated circuit to the flexible substrate, and bending a flexible extension over the stacking module integrated circuit; and molding a package body on the integrated circuit substrate and the internal stacking module.
    Type: Grant
    Filed: July 31, 2012
    Date of Patent: May 12, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Seng Guan Chow, Heap Hoe Kuan, Reza Argenty Pagaila