Patents by Inventor Heap Hoe Kuan

Heap Hoe Kuan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit package system with image sensor system
    Patent number: 7723146
    Abstract: An integrated circuit package system is provided including providing a wafer including image sensor systems having interconnects connected thereto and encapsulating the image sensor systems and interconnects in a transparent encapsulant. The system includes removing a portion of the transparent encapsulant to expose portions of the interconnects and singulating the wafer to form image sensor devices including at least one of the image sensor systems and a number of the interconnects.
    Type: Grant
    Filed: January 4, 2006
    Date of Patent: May 25, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Seng Guan Chow, Heap Hoe Kuan
  • Package-on-package using through-hole via die on saw streets
    Patent number: 7723159
    Abstract: A semiconductor package-on-package (PoP) device includes a first die incorporating a through-hole via (THV) disposed along a peripheral surface of the first die. The first die is disposed over a substrate or leadframe structure. A first semiconductor package is electrically connected to the THV of the first die, or electrically connected to the substrate or leadframe structure. An encapsulant is formed over a portion of the first die and the first semiconductor package.
    Type: Grant
    Filed: June 26, 2007
    Date of Patent: May 25, 2010
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Byung Tai Do, Heap Hoe Kuan, Seng Guan Chow
  • INTEGRATED CIRCUIT PACKAGING SYSTEM WITH MULTI LEVEL CONTACT AND METHOD OF MANUFACTURE THEREOF
    Publication number: 20100123251
    Abstract: A method of manufacture of an integrated circuit packaging system includes: forming a first level contact on a first external connection level; forming a second level contact on a second external connection level next to the first external connection level; attaching a device adjacent the first level contact and the second level contact; attaching a first level device connector to the first level contact and the device; attaching a second level device connector to the second level contact and the device; and forming an encapsulant over the first level contact, the second level contact, the first level device connector, and the second level device connector.
    Type: Application
    Filed: November 19, 2008
    Publication date: May 20, 2010
    Inventors: Seng Guan Chow, Heap Hoe Kuan, Rui Huang
  • Integrated circuit package-on-package stacking system and method of manufacture thereof
    Patent number: 7718472
    Abstract: An integrated circuit package-on-package stacking method includes forming a leadframe interposer including: forming a leadframe having a lead; forming a molded base only supporting the lead; and singulating the leadframe interposer from the leadframe.
    Type: Grant
    Filed: March 24, 2009
    Date of Patent: May 18, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Dioscoro A. Merilo, Heap Hoe Kuan, You Yang Ong, Seng Guan Chow, Ma. Shirley Asoy
  • Integrated circuit package system with package integration
    Patent number: 7709944
    Abstract: An integrated circuit package system comprising: providing a package substrate; attaching a base package having a portion of the base package substantially exposed over the package substrate; forming a cavity through the package substrate to the base package; and attaching a device partially in the cavity and connected to the portion of the base package substantially exposed.
    Type: Grant
    Filed: December 18, 2007
    Date of Patent: May 4, 2010
    Assignee: STATS ChipPac Ltd.
    Inventors: Heap Hoe Kuan, Seng Guan Chow, Linda Pei Ee Chua, Dioscoro A. Merilo
  • SEMICONDUCTOR PACKAGE SYSTEM WITH CAVITY SUBSTRATE AND MANUFACTURING METHOD THEREFOR
    Publication number: 20100102458
    Abstract: A method of manufacturing a semiconductor package system includes: providing a first substrate; providing a second substrate having a cavity, the second substrate being attached to the first substrate; connecting the first substrate to the second substrate using an interconnect, the interconnect being in the cavity; and attaching a semiconductor device to the first substrate or the second substrate.
    Type: Application
    Filed: October 28, 2008
    Publication date: April 29, 2010
    Inventors: Seng Guan Chow, Rui Huang, Heap Hoe Kuan
  • Semiconductor device and method of forming recessed conductive vias in saw streets
    Patent number: 7704796
    Abstract: A semiconductor die has an insulating material disposed in a peripheral region around the die. A blind via is formed through the gap. A conductive material is deposited in the blind via to form a conductive via. A conductive layer is formed between the conductive via and contact pad on the semiconductor die. A protective layer is formed over the front side of the semiconductor die. A portion of the insulating material and conductive via is removed from a backside of the semiconductor die opposite the front side of the semiconductor die so that a thickness of the conductive via is less than a thickness of the semiconductor wafer. The insulating material and conductive via are tapered. The wafer is singulated through the gap to separate the semiconductor die. A plurality of semiconductor die can be stacked and electrically interconnected through the conductive vias.
    Type: Grant
    Filed: June 4, 2008
    Date of Patent: April 27, 2010
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Reza A. Pagaila, Byung Tai Do, Heap Hoe Kuan
  • Semiconductor Device and Method of Forming Stepped-Down RDL and Recessed THV in Peripheral Region of the Device
    Publication number: 20100096731
    Abstract: A semiconductor die has a peripheral region around the die. An insulating layer is formed over the semiconductor die. A portion of the insulating layer and peripheral is removed to form a recess around the semiconductor die. A conductive layer is deposited over the insulating layer and recess. The conductive layer is electrically connected to contact pads on the semiconductor die and conforms to a step into the recess. A gap is created through the conductive layer and peripheral region around the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a through hole via (THV). A conductive material is deposited in the THV to form a conductive THV. The conductive THV is recessed with respect to a surface of the semiconductor die. The conductive THV is electrically connected to the conductive layer.
    Type: Application
    Filed: December 18, 2009
    Publication date: April 22, 2010
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Byung Tai Do, Heap Hoe Kuan, Reza A. Pagaila, Linda Pei Ee Chua
  • Integrated circuit package system employing wafer level chip scale packaging
    Patent number: 7700458
    Abstract: An integrated circuit package system that includes: providing a substrate with a protective coating; attaching a labeling film to a support member in a separate process; joining the protective coating and the labeling film; and dicing the substrate, the protective coating, and the labeling film to form the integrated circuit package system.
    Type: Grant
    Filed: August 4, 2006
    Date of Patent: April 20, 2010
    Assignee: Stats Chippac Ltd.
    Inventors: Byung Tai Do, Heap Hoe Kuan
  • MULTI-CHIP PACKAGE SYSTEM INCORPORATING AN INTERNAL STACKING MODULE WITH SUPPORT PROTRUSIONS
    Publication number: 20100090350
    Abstract: The present invention provides a multi-chip package system that includes: providing a package substrate; attaching a base semiconductor die to the package substrate; connecting an interconnect between the base semiconductor die and the package substrate; and encapsulating at least portions of the package substrate, the base semiconductor die, and the interconnect with an encapsulant defining a support protrusion adjacent to the interconnect and substantially perpendicular to the package substrate, a cavity bounded by the support protrusion, and a gap linking the cavity to the edge of the encapsulant.
    Type: Application
    Filed: October 9, 2008
    Publication date: April 15, 2010
    Inventors: Seng Guan Chow, Heap Hoe Kuan, Rui Huang
  • INTEGRATED CIRCUIT PACKAGE SYSTEM WITH MOUNTING STRUCTURE
    Publication number: 20100078828
    Abstract: An integrated circuit package system includes: providing a mountable structure having a contact pad and an inner pad; mounting an integrated circuit device having a linear through channel over the mountable structure with the linear through channel traversing between an integrated circuit device first side and an integrated circuit device second side; and connecting the linear through channel exposed on the integrated circuit device second side to the inner pad.
    Type: Application
    Filed: September 27, 2008
    Publication date: April 1, 2010
    Inventors: Rui Huang, Seng Guan Chow, Heap Hoe Kuan
  • Extended redistribution layers bumped wafer
    Patent number: 7687318
    Abstract: A semiconductor device is manufactured by, first, providing a wafer, designated with a saw street guide, and having a bond pad formed on an active surface of the wafer. The wafer is taped with a dicing tape. The wafer is singulated along the saw street guide into a plurality of dies having a plurality of gaps between each of the plurality of dies. The dicing tape is stretched to expand the plurality of gaps to a predetermined distance. An organic material is deposited into each of the plurality of gaps. A top surface of the organic material is substantially coplanar with a top surface of a first die of the plurality of dies. A redistribution layer is patterned over a portion of the organic material. An under bump metallization (UBM) is deposited over the organic material in electrical communication, through the redistribution layer, with the bond pad.
    Type: Grant
    Filed: May 4, 2007
    Date of Patent: March 30, 2010
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Byung Tai Do, Heap Hoe Kuan
  • INTEGRATED CIRCUIT PACKAGING SYSTEM HAVING PLANAR INTERCONNECT
    Publication number: 20100072596
    Abstract: An integrated circuit package system includes: mounting an integrated circuit, having a planar interconnect, over a carrier with the planar interconnect at a non-active side of the integrated circuit and an active side of the integrated circuit facing the carrier; connecting the integrated circuit and the carrier; connecting the planar interconnect and the carrier; and forming an encapsulation over the integrated circuit, the carrier, and the planar interconnect.
    Type: Application
    Filed: September 25, 2008
    Publication date: March 25, 2010
    Inventors: Reza Argenty Pagaila, Byung Tai Do, Heap Hoe Kuan
  • INTEGRATED CIRCUIT PACKAGE SYSTEM FOR STACKABLE DEVICES
    Publication number: 20100072597
    Abstract: An integrated circuit package system provides: forming a stack module including: providing a stack die and encapsulating the stack die with an insulating material having a protruding support and a pad connected to the stack die; mounting the stack module on a package base; connecting the pad to the package base; mounting a top die on the protruding support; connecting the top die to the package base; and encapsulating the top die, the package base, and the stack module with a package encapsulant.
    Type: Application
    Filed: September 25, 2008
    Publication date: March 25, 2010
    Inventors: Seng Guan Chow, Rui Huang, Heap Hoe Kuan
  • INTEGRATED CIRCUIT PACKAGE SYSTEM WITH IMAGE SENSOR SYSTEM
    Publication number: 20100065936
    Abstract: An integrated circuit package system is provided including providing a wafer including image sensor systems having interconnects connected thereto and encapsulating the image sensor systems and interconnects in a transparent encapsulant. The system includes removing a portion of the transparent encapsulant to expose portions of the interconnects and singulating the wafer to form image sensor devices including at least one of the image sensor systems and a number of the interconnects.
    Type: Application
    Filed: November 20, 2009
    Publication date: March 18, 2010
    Inventors: Seng Guan Chow, Heap Hoe Kuan
  • INTEGRATED CIRCUIT PACKAGE SYSTEM WITH REDISTRIBUTION LAYER
    Publication number: 20100059885
    Abstract: An integrated circuit package system includes: providing a base device; attaching a base interconnect to the base device; applying an encapsulant over the base device and the base interconnect; and forming a re-routing film over the encapsulant, the base device, and the base interconnect for connectivity without a substrate.
    Type: Application
    Filed: September 9, 2008
    Publication date: March 11, 2010
    Inventors: Heap Hoe Kuan, Seng Guan Chow, Rui Huang
  • LEADLESS SEMICONDUCTOR CHIP CARRIER SYSTEM
    Publication number: 20100059884
    Abstract: A semiconductor package system includes: providing a semiconductor die with bonding pad on the semiconductor die; attaching the semiconductor die to an intermediate layer; attaching one end of a bonding wire to the bonding pad; forming a bonding ball at the other end of the bonding wire, the bonding ball being fully or partially embedded in the intermediate layer; encapsulating the semiconductor die, the bonding pad, the bonding wire, and a portion of the bonding ball with a mold compound; removing the intermediate layer, resulting in the bonding ball protruding from the exposed mold compound bottom surface; and conditioning the bonding ball
    Type: Application
    Filed: September 5, 2008
    Publication date: March 11, 2010
    Inventors: Heap Hoe Kuan, Rui Huang, Seng Guan Chow
  • Leaded stacked packages having integrated upper lead
    Patent number: 7667308
    Abstract: A semiconductor package includes a leadframe. An upper lead is disposed above the leadframe. A first die is attached to a lower surface of the upper lead to provide electrical conductivity from the first die to the upper lead. A second die is attached to the first die. A method of manufacturing a semiconductor package includes providing a leadframe having an upper lead, lower lead, and an elevated die paddle. A first die, attached to a plurality of dies in a wafer form, is attached to a second die. The first die is singulated from the plurality of dies. The first and second dies are attached to the elevated die paddle structure. The first die is wire bonded to the lower lead. An encapsulant is formed over the first and second dies. The elevated die paddle is removed to expose a surface of the upper lead and second die.
    Type: Grant
    Filed: July 24, 2006
    Date of Patent: February 23, 2010
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Byung Tai Do, Francis Heap Hoe Kuan, Seng Guan Chow
  • SEMICONDUCTOR ASSEMBLY WITH COMPONENT ATTACHED ON DIE BACK SIDE
    Publication number: 20100032828
    Abstract: One or more electronic components can be mounted on the back side of a semiconductor die. The components can be passive components, active components, or combinations thereof. The components can be soldered to signal routes on the back side of the die, the signal routes being attached to the die using a metallization layer or using one or more dielectric layer sections. Placing components on the back side of the die can allow for incorporation of the components without necessarily increasing the form factor of the die's package.
    Type: Application
    Filed: October 12, 2009
    Publication date: February 11, 2010
    Inventors: Seng Guan Chow, Francis Heap Hoe Kuan
  • Semiconductor device and method of forming stepped-down RDL and recessed THV in peripheral region of the device
    Patent number: 7659145
    Abstract: A semiconductor die has a peripheral region around the die. An insulating layer is formed over the semiconductor die. A portion of the insulating layer and peripheral is removed to form a recess around the semiconductor die. A conductive layer is deposited over the insulating layer and recess. The conductive layer is electrically connected to contact pads on the semiconductor die and conforms to a step into the recess. A gap is created through the conductive layer and peripheral region around the semiconductor die. An insulating material is deposited in the gap. A portion of the insulating material is removed to form a through hole via (THV). A conductive material is deposited in the THV to form a conductive THV. The conductive THV is recessed with respect to a surface of the semiconductor die. The conductive THV is electrically connected to the conductive layer.
    Type: Grant
    Filed: July 14, 2008
    Date of Patent: February 9, 2010
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Byung Tai Do, Heap Hoe Kuan, Reza A. Pagaila, Linda Pei Ee Chua