Patents by Inventor Heather L. Hanson

Heather L. Hanson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11073891
    Abstract: A distributed power management system is configured determine a node power consumption of a node during a first time interval. The system can determine a node power cap. The system can determine a proportional component power budget for a component of the node based, at least in part, on the node power consumption and a component power consumption. The system can determine a power budget for the component for a second time interval based, at least in part on the proportional component power budget.
    Type: Grant
    Filed: May 10, 2019
    Date of Patent: July 27, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alan Drake, Guillermo J. Silva, Timothy G. Hallett, Heather L. Hanson, Jordan Keuseman, Charles R. Lefurgy, Karthick Rajamani, Todd J. Rosedahl, Malcolm S. Allen-Ware
  • Publication number: 20190272019
    Abstract: A distributed power management system is configured determine a node power consumption of a node during a first time interval. The system can determine a node power cap. The system can determine a proportional component power budget for a component of the node based, at least in part, on the node power consumption and a component power consumption. The system can determine a power budget for the component for a second time interval based, at least in part on the proportional component power budget.
    Type: Application
    Filed: May 10, 2019
    Publication date: September 5, 2019
    Inventors: Alan Drake, Guillermo J. Silva, Timothy G. Hallett, Heather L. Hanson, Jordan Keuseman, Charles R. Lefurgy, Karthick Rajamani, Todd J. Rosedahl, Malcolm S. Allen-Ware
  • Patent number: 10331192
    Abstract: A distributed power management system is configured determine a node power consumption of a node during a first time interval. The system can determine a node power cap. The system can determine a proportional component power budget for a component of the node based, at least in part, on the node power consumption and a component power consumption. The system can determine a power budget for the component for a second time interval based, at least in part on the proportional component power budget.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: June 25, 2019
    Assignee: International Business Machines Corporation
    Inventors: Alan Drake, Guillermo J. Silva, Timothy G. Hallett, Heather L. Hanson, Jordan Keuseman, Charles R. Lefurgy, Karthick Rajamani, Todd J. Rosedahl, Malcolm S. Allen-Ware
  • Patent number: 10241889
    Abstract: A processor system tracks, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising multiple cycles. The processor system evaluates an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions for executing at least one operation tracked in the at least one counter during the interval.
    Type: Grant
    Filed: March 8, 2017
    Date of Patent: March 26, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Heather L. Hanson, Venkat R. Indukuru, Francis P. O'Connell, Karthick Rajamani
  • Publication number: 20170177275
    Abstract: A processor system tracks, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising multiple cycles. The processor system evaluates an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions for executing at least one operation tracked in the at least one counter during the interval.
    Type: Application
    Filed: March 8, 2017
    Publication date: June 22, 2017
    Inventors: HEATHER L. HANSON, VENKAT R. INDUKURU, FRANCIS P. O'CONNELL, KARTHICK RAJAMANI
  • Patent number: 9652356
    Abstract: A processor system tracks, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising multiple cycles. The processor system evaluates an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions for executing at least one operation tracked in the at least one counter during the interval.
    Type: Grant
    Filed: May 28, 2015
    Date of Patent: May 16, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Heather L. Hanson, Venkat R. Indukuru, Francis P. O'Connell, Karthick Rajamani
  • Patent number: 9600392
    Abstract: A processor system tracks, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising multiple cycles. The processor system evaluates an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions for executing at least one operation tracked in the at least one counter during the interval.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: March 21, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Heather L. Hanson, Venkat R. Indukuru, Francis P. O'Connell, Karthick Rajamani
  • Patent number: 9541985
    Abstract: A mechanism is provided for optimizing energy efficiency in a set of processor cores while maintaining application performance for a set of applications. A quality of service (QoS) level is received for one or more active applications in the set of applications and state information associated with each processor core in the set of processor cores is identified. Responsive to the QoS level and the state information indicating an action to be implemented, a change is implemented to reduce power utilization by one or more processor cores in the set of processor cores in the data processing system, where the change is via at least one of dynamic frequency scaling, dynamic voltage scaling, or core folding.
    Type: Grant
    Filed: December 12, 2013
    Date of Patent: January 10, 2017
    Assignee: International Business Machines Corporation
    Inventors: Malcolm S. Allen-Ware, Heather L. Hanson, David J. Palframan, Srinivasan Ramani, Ken V. Vu
  • Patent number: 9535486
    Abstract: A mechanism is provided for optimizing energy efficiency in a set of processor cores while maintaining application performance for a set of applications. A quality of service (QoS) level is received for one or more active applications in the set of applications and state information associated with each processor core in the set of processor cores is identified. Responsive to the QoS level and the state information indicating an action to be implemented, a change is implemented to reduce power utilization by one or more processor cores in the set of processor cores in the data processing system, where the change is via at least one of dynamic frequency scaling, dynamic voltage scaling, or core folding.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: January 3, 2017
    Assignee: International Business Machines Corporation
    Inventors: Malcolm S. Allen-Ware, Heather L. Hanson, David J. Palframan, Srinivasan Ramani, Ken V. Vu
  • Patent number: 9354943
    Abstract: According to an aspect, power management of a multi-core processing system includes determining workload characteristics in the multi-core processing system. A power adjustment scenario is identified based on the workload characteristics. A predetermined actuation order for at least two power adjustment actuators is identified based on the power adjustment scenario. Based on the predetermined actuation order, it is determined whether there is an adequate adjustment capacity for a power adjustment action associated with one of the at least two power adjustment actuators. The power adjustment action is initiated based on the predetermined actuation order and determining that the adequate adjustment capacity is available.
    Type: Grant
    Filed: March 19, 2014
    Date of Patent: May 31, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Michael S. Floyd, Heather L. Hanson, Hans M. Jacobson, Karthick Rajamani, Srinivasan Ramani, Todd J. Rosedahl, Augusto J. Vega
  • Publication number: 20160124486
    Abstract: A distributed power management system is configured determine a node power consumption of a node during a first time interval. The system can determine a node power cap. The system can determine a proportional component power budget for a component of the node based, at least in part, on the node power consumption and a component power consumption. The system can determine a power budget for the component for a second time interval based, at least in part on the proportional component power budget.
    Type: Application
    Filed: January 13, 2016
    Publication date: May 5, 2016
    Inventors: Alan Drake, Guillermo J. Silva, Timothy G. Hallett, Heather L. Hanson, Jordan Keuseman, Charles R. Lefurgy, Karthick Rajamani, Todd J. Rosedahl, Malcolm S. Allen-Ware
  • Patent number: 9298247
    Abstract: A distributed power management computer program product is configured to collect power consumption data that indicates power consumption by at least a plurality of the components of a node. The program code can be configured to provide, to each of a plurality of controllers associated with a respective one of the plurality of components, the power consumption data. The program code can be configured to determine a node power consumption. The program code can be configured to determine a power differential as a difference between the node power consumption and an upper power consumption threshold of the node. The program code can be configured to determine a proportion of the node power consumption consumed by a first component. The program code can be configured to compute a local power budget for the first component.
    Type: Grant
    Filed: November 27, 2012
    Date of Patent: March 29, 2016
    Assignee: International Business Machines Corporation
    Inventors: Alan Drake, Guillermo J. Silva, Timothy G. Hallett, Heather L. Hanson, Jordan Keuseman, Charles R. Lefurgy, Karthick Rajamani, Todd J. Rosedahl, Malcom S. Allen-Ware
  • Patent number: 9292662
    Abstract: A method, system, and computer program product for reducing power and energy consumption in a server system with multiple processor cores is disclosed. The system may include an operating system for scheduling user workloads among a processor pool. The processor pool may include active licensed processor cores and inactive unlicensed processor cores. The method and computer program product may reduce power and energy consumption by including steps and sets of instructions activating spare cores and adjusting the operating frequency of processor cores, including the newly activated spare cores to provide equivalent computing resources as the original licensed cores operating at a specified clock frequency.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: March 22, 2016
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Elmootazbellah N. Elnozahy, Heather L. Hanson, Freeman L. Rawson, III, Malcolm S. Ware
  • Patent number: 9292074
    Abstract: Embodiments include collecting, from each of a plurality of controllers of a node having a plurality of components, component power consumption. Each of the plurality of controllers is associated with one or more of the components. The component power consumptions are provided to the controllers. A node power consumption for the node is determined based, at least in part, on the component power consumption. The power cap is determined for the plurality of components. A power differential power is determined as a difference between the node power consumption and the power cap for the plurality of components. A proportion of the node power consumption consumed by the component is determined based on the component power consumption of the component. A local power budget is computed for the component based, at least in part, on the power differential and the proportion of the node power consumption consumed by the component.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: March 22, 2016
    Assignee: International Business Machines Corporation
    Inventors: Malcolm S. Allen-Ware, Alan Drake, Timothy G. Hallett, Heather L. Hanson, Jordan Keuseman, Charles R. Lefurgy, Karthick Rajamani, Todd J. Rosedahl, Guillermo J. Silva
  • Publication number: 20160041775
    Abstract: A processor system tracks, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising multiple cycles. The processor system evaluates an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions for executing at least one operation tracked in the at least one counter during the interval.
    Type: Application
    Filed: May 28, 2015
    Publication date: February 11, 2016
    Inventors: HEATHER L. HANSON, VENKAT R. INDUKURU, FRANCIS P. O'CONNELL, KARTHICK RAJAMANI
  • Publication number: 20160041594
    Abstract: A processor system tracks, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising multiple cycles. The processor system evaluates an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions for executing at least one operation tracked in the at least one counter during the interval.
    Type: Application
    Filed: August 11, 2014
    Publication date: February 11, 2016
    Inventors: HEATHER L. HANSON, VENKAT R. INDUKURU, FRANCIS P. O'CONNELL, KARTHICK RAJAMANI
  • Patent number: 9256273
    Abstract: Embodiments include collecting, from each of a plurality of controllers of a node having a plurality of components, component power consumption. Each of the plurality of controllers is associated with one or more of the components. The component power consumptions are provided to the controllers. A node power consumption for the node is determined based, at least in part, on the component power consumption. The power cap is determined for the plurality of components. A power differential power is determined as a difference between the node power consumption and the power cap for the plurality of components. A proportion of the node power consumption consumed by the component is determined based on the component power consumption of the component. A local power budget is computed for the component based, at least in part, on the power differential and the proportion of the node power consumption consumed by the component.
    Type: Grant
    Filed: February 8, 2013
    Date of Patent: February 9, 2016
    Assignee: International Business Machines Corporation
    Inventors: Malcolm S. Allen-Ware, Alan Drake, Timothy G. Hallett, Heather L. Hanson, Jordan Keuseman, Charles R. Lefurgy, Karthick Rajamani, Todd J. Rosedahl, Guillermo J. Silva
  • Publication number: 20150268710
    Abstract: According to an aspect, power management of a multi-core processing system includes determining workload characteristics in the multi-core processing system. A power adjustment scenario is identified based on the workload characteristics. A predetermined actuation order for at least two power adjustment actuators is identified based on the power adjustment scenario. Based on the predetermined actuation order, it is determined whether there is an adequate adjustment capacity for a power adjustment action associated with one of the at least two power adjustment actuators. The power adjustment action is initiated based on the predetermined actuation order and determining that the adequate adjustment capacity is available.
    Type: Application
    Filed: March 19, 2014
    Publication date: September 24, 2015
    Applicant: International Business Machines Corporation
    Inventors: Pradip Bose, Alper Buyuktosunoglu, Michael S. Floyd, Heather L. Hanson, Hans M. Jacobson, Karthick Rajamani, Srinivasan Ramani, Todd J. Rosedahl, Augusto J. Vega
  • Publication number: 20150169032
    Abstract: A mechanism is provided for optimizing energy efficiency in a set of processor cores while maintaining application performance for a set of applications. A quality of sendee (QoS) level is received for one or more active applications in the set of applications and state information associated with each processor core in the set of processor cores is identified. Responsive to the QoS level and die state information indicating an action to be implemented, a change is implemented to reduce power utilization by one or more processor cores in the set of processor cores in the data processing system, where the change is via at least one of dynamic frequency scaling, dynamic voltage scaling, or core folding.
    Type: Application
    Filed: December 12, 2013
    Publication date: June 18, 2015
    Applicant: International Business Machines Corporation
    Inventors: Malcolm S. Allen-Ware, Heather L. Hanson, David J. Palframan, Srinivasan Ramani, Ken V. Vu
  • Publication number: 20150169035
    Abstract: A mechanism is provided for optimizing energy efficiency in a set of processor cores while maintaining application performance for a set of applications. A quality of service (QoS) level is received for one or more active applications in the set of applications and state information associated with each processor core in the set of processor cores is identified. Responsive to the QoS level and the state information indicating an action to be implemented, a change is implemented to reduce power utilization by one or more processor cores in the set of processor cores in the data processing system, where the change is via at least one of dynamic frequency scaling, dynamic voltage scaling, or core folding.
    Type: Application
    Filed: June 13, 2014
    Publication date: June 18, 2015
    Inventors: Malcolm S. Allen-Ware, Heather L. Hanson, David J. Palframan, Srinivasan Ramani, Ken V. Vu