Patents by Inventor Heather L. Hanson
Heather L. Hanson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11073891Abstract: A distributed power management system is configured determine a node power consumption of a node during a first time interval. The system can determine a node power cap. The system can determine a proportional component power budget for a component of the node based, at least in part, on the node power consumption and a component power consumption. The system can determine a power budget for the component for a second time interval based, at least in part on the proportional component power budget.Type: GrantFiled: May 10, 2019Date of Patent: July 27, 2021Assignee: International Business Machines CorporationInventors: Alan Drake, Guillermo J. Silva, Timothy G. Hallett, Heather L. Hanson, Jordan Keuseman, Charles R. Lefurgy, Karthick Rajamani, Todd J. Rosedahl, Malcolm S. Allen-Ware
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Publication number: 20190272019Abstract: A distributed power management system is configured determine a node power consumption of a node during a first time interval. The system can determine a node power cap. The system can determine a proportional component power budget for a component of the node based, at least in part, on the node power consumption and a component power consumption. The system can determine a power budget for the component for a second time interval based, at least in part on the proportional component power budget.Type: ApplicationFiled: May 10, 2019Publication date: September 5, 2019Inventors: Alan Drake, Guillermo J. Silva, Timothy G. Hallett, Heather L. Hanson, Jordan Keuseman, Charles R. Lefurgy, Karthick Rajamani, Todd J. Rosedahl, Malcolm S. Allen-Ware
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Patent number: 10331192Abstract: A distributed power management system is configured determine a node power consumption of a node during a first time interval. The system can determine a node power cap. The system can determine a proportional component power budget for a component of the node based, at least in part, on the node power consumption and a component power consumption. The system can determine a power budget for the component for a second time interval based, at least in part on the proportional component power budget.Type: GrantFiled: January 13, 2016Date of Patent: June 25, 2019Assignee: International Business Machines CorporationInventors: Alan Drake, Guillermo J. Silva, Timothy G. Hallett, Heather L. Hanson, Jordan Keuseman, Charles R. Lefurgy, Karthick Rajamani, Todd J. Rosedahl, Malcolm S. Allen-Ware
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Patent number: 10241889Abstract: A processor system tracks, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising multiple cycles. The processor system evaluates an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions for executing at least one operation tracked in the at least one counter during the interval.Type: GrantFiled: March 8, 2017Date of Patent: March 26, 2019Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Heather L. Hanson, Venkat R. Indukuru, Francis P. O'Connell, Karthick Rajamani
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Publication number: 20170177275Abstract: A processor system tracks, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising multiple cycles. The processor system evaluates an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions for executing at least one operation tracked in the at least one counter during the interval.Type: ApplicationFiled: March 8, 2017Publication date: June 22, 2017Inventors: HEATHER L. HANSON, VENKAT R. INDUKURU, FRANCIS P. O'CONNELL, KARTHICK RAJAMANI
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Patent number: 9652356Abstract: A processor system tracks, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising multiple cycles. The processor system evaluates an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions for executing at least one operation tracked in the at least one counter during the interval.Type: GrantFiled: May 28, 2015Date of Patent: May 16, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Heather L. Hanson, Venkat R. Indukuru, Francis P. O'Connell, Karthick Rajamani
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Patent number: 9600392Abstract: A processor system tracks, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising multiple cycles. The processor system evaluates an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions for executing at least one operation tracked in the at least one counter during the interval.Type: GrantFiled: August 11, 2014Date of Patent: March 21, 2017Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Heather L. Hanson, Venkat R. Indukuru, Francis P. O'Connell, Karthick Rajamani
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Patent number: 9541985Abstract: A mechanism is provided for optimizing energy efficiency in a set of processor cores while maintaining application performance for a set of applications. A quality of service (QoS) level is received for one or more active applications in the set of applications and state information associated with each processor core in the set of processor cores is identified. Responsive to the QoS level and the state information indicating an action to be implemented, a change is implemented to reduce power utilization by one or more processor cores in the set of processor cores in the data processing system, where the change is via at least one of dynamic frequency scaling, dynamic voltage scaling, or core folding.Type: GrantFiled: December 12, 2013Date of Patent: January 10, 2017Assignee: International Business Machines CorporationInventors: Malcolm S. Allen-Ware, Heather L. Hanson, David J. Palframan, Srinivasan Ramani, Ken V. Vu
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Patent number: 9535486Abstract: A mechanism is provided for optimizing energy efficiency in a set of processor cores while maintaining application performance for a set of applications. A quality of service (QoS) level is received for one or more active applications in the set of applications and state information associated with each processor core in the set of processor cores is identified. Responsive to the QoS level and the state information indicating an action to be implemented, a change is implemented to reduce power utilization by one or more processor cores in the set of processor cores in the data processing system, where the change is via at least one of dynamic frequency scaling, dynamic voltage scaling, or core folding.Type: GrantFiled: June 13, 2014Date of Patent: January 3, 2017Assignee: International Business Machines CorporationInventors: Malcolm S. Allen-Ware, Heather L. Hanson, David J. Palframan, Srinivasan Ramani, Ken V. Vu
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Patent number: 9354943Abstract: According to an aspect, power management of a multi-core processing system includes determining workload characteristics in the multi-core processing system. A power adjustment scenario is identified based on the workload characteristics. A predetermined actuation order for at least two power adjustment actuators is identified based on the power adjustment scenario. Based on the predetermined actuation order, it is determined whether there is an adequate adjustment capacity for a power adjustment action associated with one of the at least two power adjustment actuators. The power adjustment action is initiated based on the predetermined actuation order and determining that the adequate adjustment capacity is available.Type: GrantFiled: March 19, 2014Date of Patent: May 31, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Pradip Bose, Alper Buyuktosunoglu, Michael S. Floyd, Heather L. Hanson, Hans M. Jacobson, Karthick Rajamani, Srinivasan Ramani, Todd J. Rosedahl, Augusto J. Vega
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Publication number: 20160124486Abstract: A distributed power management system is configured determine a node power consumption of a node during a first time interval. The system can determine a node power cap. The system can determine a proportional component power budget for a component of the node based, at least in part, on the node power consumption and a component power consumption. The system can determine a power budget for the component for a second time interval based, at least in part on the proportional component power budget.Type: ApplicationFiled: January 13, 2016Publication date: May 5, 2016Inventors: Alan Drake, Guillermo J. Silva, Timothy G. Hallett, Heather L. Hanson, Jordan Keuseman, Charles R. Lefurgy, Karthick Rajamani, Todd J. Rosedahl, Malcolm S. Allen-Ware
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Patent number: 9298247Abstract: A distributed power management computer program product is configured to collect power consumption data that indicates power consumption by at least a plurality of the components of a node. The program code can be configured to provide, to each of a plurality of controllers associated with a respective one of the plurality of components, the power consumption data. The program code can be configured to determine a node power consumption. The program code can be configured to determine a power differential as a difference between the node power consumption and an upper power consumption threshold of the node. The program code can be configured to determine a proportion of the node power consumption consumed by a first component. The program code can be configured to compute a local power budget for the first component.Type: GrantFiled: November 27, 2012Date of Patent: March 29, 2016Assignee: International Business Machines CorporationInventors: Alan Drake, Guillermo J. Silva, Timothy G. Hallett, Heather L. Hanson, Jordan Keuseman, Charles R. Lefurgy, Karthick Rajamani, Todd J. Rosedahl, Malcom S. Allen-Ware
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Patent number: 9292662Abstract: A method, system, and computer program product for reducing power and energy consumption in a server system with multiple processor cores is disclosed. The system may include an operating system for scheduling user workloads among a processor pool. The processor pool may include active licensed processor cores and inactive unlicensed processor cores. The method and computer program product may reduce power and energy consumption by including steps and sets of instructions activating spare cores and adjusting the operating frequency of processor cores, including the newly activated spare cores to provide equivalent computing resources as the original licensed cores operating at a specified clock frequency.Type: GrantFiled: December 17, 2009Date of Patent: March 22, 2016Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Elmootazbellah N. Elnozahy, Heather L. Hanson, Freeman L. Rawson, III, Malcolm S. Ware
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Patent number: 9292074Abstract: Embodiments include collecting, from each of a plurality of controllers of a node having a plurality of components, component power consumption. Each of the plurality of controllers is associated with one or more of the components. The component power consumptions are provided to the controllers. A node power consumption for the node is determined based, at least in part, on the component power consumption. The power cap is determined for the plurality of components. A power differential power is determined as a difference between the node power consumption and the power cap for the plurality of components. A proportion of the node power consumption consumed by the component is determined based on the component power consumption of the component. A local power budget is computed for the component based, at least in part, on the power differential and the proportion of the node power consumption consumed by the component.Type: GrantFiled: February 8, 2013Date of Patent: March 22, 2016Assignee: International Business Machines CorporationInventors: Malcolm S. Allen-Ware, Alan Drake, Timothy G. Hallett, Heather L. Hanson, Jordan Keuseman, Charles R. Lefurgy, Karthick Rajamani, Todd J. Rosedahl, Guillermo J. Silva
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Publication number: 20160041775Abstract: A processor system tracks, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising multiple cycles. The processor system evaluates an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions for executing at least one operation tracked in the at least one counter during the interval.Type: ApplicationFiled: May 28, 2015Publication date: February 11, 2016Inventors: HEATHER L. HANSON, VENKAT R. INDUKURU, FRANCIS P. O'CONNELL, KARTHICK RAJAMANI
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Publication number: 20160041594Abstract: A processor system tracks, in at least one counter, a number of cycles in which at least one execution unit of at least one processor core is idle and at least one thread of the at least one processor core is waiting on at least one off-core memory access during run-time of the at least one processor core during an interval comprising multiple cycles. The processor system evaluates an expected performance impact of a frequency change within the at least one processor core based on the current run-time conditions for executing at least one operation tracked in the at least one counter during the interval.Type: ApplicationFiled: August 11, 2014Publication date: February 11, 2016Inventors: HEATHER L. HANSON, VENKAT R. INDUKURU, FRANCIS P. O'CONNELL, KARTHICK RAJAMANI
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Patent number: 9256273Abstract: Embodiments include collecting, from each of a plurality of controllers of a node having a plurality of components, component power consumption. Each of the plurality of controllers is associated with one or more of the components. The component power consumptions are provided to the controllers. A node power consumption for the node is determined based, at least in part, on the component power consumption. The power cap is determined for the plurality of components. A power differential power is determined as a difference between the node power consumption and the power cap for the plurality of components. A proportion of the node power consumption consumed by the component is determined based on the component power consumption of the component. A local power budget is computed for the component based, at least in part, on the power differential and the proportion of the node power consumption consumed by the component.Type: GrantFiled: February 8, 2013Date of Patent: February 9, 2016Assignee: International Business Machines CorporationInventors: Malcolm S. Allen-Ware, Alan Drake, Timothy G. Hallett, Heather L. Hanson, Jordan Keuseman, Charles R. Lefurgy, Karthick Rajamani, Todd J. Rosedahl, Guillermo J. Silva
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Publication number: 20150268710Abstract: According to an aspect, power management of a multi-core processing system includes determining workload characteristics in the multi-core processing system. A power adjustment scenario is identified based on the workload characteristics. A predetermined actuation order for at least two power adjustment actuators is identified based on the power adjustment scenario. Based on the predetermined actuation order, it is determined whether there is an adequate adjustment capacity for a power adjustment action associated with one of the at least two power adjustment actuators. The power adjustment action is initiated based on the predetermined actuation order and determining that the adequate adjustment capacity is available.Type: ApplicationFiled: March 19, 2014Publication date: September 24, 2015Applicant: International Business Machines CorporationInventors: Pradip Bose, Alper Buyuktosunoglu, Michael S. Floyd, Heather L. Hanson, Hans M. Jacobson, Karthick Rajamani, Srinivasan Ramani, Todd J. Rosedahl, Augusto J. Vega
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Publication number: 20150169035Abstract: A mechanism is provided for optimizing energy efficiency in a set of processor cores while maintaining application performance for a set of applications. A quality of service (QoS) level is received for one or more active applications in the set of applications and state information associated with each processor core in the set of processor cores is identified. Responsive to the QoS level and the state information indicating an action to be implemented, a change is implemented to reduce power utilization by one or more processor cores in the set of processor cores in the data processing system, where the change is via at least one of dynamic frequency scaling, dynamic voltage scaling, or core folding.Type: ApplicationFiled: June 13, 2014Publication date: June 18, 2015Inventors: Malcolm S. Allen-Ware, Heather L. Hanson, David J. Palframan, Srinivasan Ramani, Ken V. Vu
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Publication number: 20150169032Abstract: A mechanism is provided for optimizing energy efficiency in a set of processor cores while maintaining application performance for a set of applications. A quality of sendee (QoS) level is received for one or more active applications in the set of applications and state information associated with each processor core in the set of processor cores is identified. Responsive to the QoS level and die state information indicating an action to be implemented, a change is implemented to reduce power utilization by one or more processor cores in the set of processor cores in the data processing system, where the change is via at least one of dynamic frequency scaling, dynamic voltage scaling, or core folding.Type: ApplicationFiled: December 12, 2013Publication date: June 18, 2015Applicant: International Business Machines CorporationInventors: Malcolm S. Allen-Ware, Heather L. Hanson, David J. Palframan, Srinivasan Ramani, Ken V. Vu