Abstract: A circuit that provides a stable predrive to a BiCMOS LVDS output which compensates for supply voltage variations while maintaining a suitably fast signal path. The supply voltage compensation circuit provides an offset to the predrive level shift such that when the supply voltage Vcc rises, the predrive output voltage is lowered in response.

Abstract: An apparatus for handling high speed data communication signals in at least one input channel. Each communication signal is encoded in signal excursions in at least one predetermined format. The apparatus includes: (a) at least one input locus coupled with each input channel for receiving the signals; (b) at least one output locus for presenting selected communication signals in a desired format in at least one output channel; and (c) a plurality of treating circuits for treating the signal excursions in a plurality of formats that include the predetermined format and the desired format. Each treating circuit is coupled with at least one respective input locus and at least one respective output locus. The apparatus presents sufficiently low capacitance between input loci and output loci to impart substantially zero time delay to the communication signals.

Abstract: A system 500 and method 900 is disclosed for a driver circuit used for high speed data transmission in LVDS transceiver device applications (e.g., LVDS repeaters and PECL/ECL to LVDS converters). The transceivers are intended to receive a low voltage differential input signal and drive an TIA/EIA-644 compliant LVDS signal. The driver circuit operates at speeds up to 1.36 Gbps, making it compatible with the OC-24 signaling rate for optical transmission. To accomplish this, the driver uses a mixed combination of voltage and current mode drive sections in the output circuit. MOS transistors and a current source are used in the current mode switch portion to switch the drive with a constant current at the high speeds, and NPN transistors in the voltage mode output portion provide variable impedance for the output circuit.

Abstract: A circuit that provides a stable predrive to a BiCMOS LVDS output which compensates for supply voltage variations while maintaining a suitably fast signal path. The supply voltage compensation circuit provides an offset to the predrive level shift such that when the supply voltage Vcc rises, the predrive output voltage is lowered in response.