Patents by Inventor Hee-Bum Hong
Hee-Bum Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11930629Abstract: Disclosed is a semiconductor memory device comprising a plurality of memory cells each including an access transistor, a pull-up transistor, and a pull-down transistor on a substrate, a first line layer on the memory cells and including a first lower landing pad and a second lower landing pad, a second line layer on the first line layer and including a ground line having an opening and an upper landing pad in the opening, and a third line layer including a word line on the second line layer. The ground line is electrically connected through the first lower landing pad to a terminal of the pull-down transistor. The word line is electrically connected through the upper landing pad and the second lower landing pad to a terminal of the access transistor.Type: GrantFiled: December 9, 2021Date of Patent: March 12, 2024Assignee: Samsung Electronics Co., Ltd.Inventors: Hee Bum Hong, Yongrae Cho
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Patent number: 11348913Abstract: A semiconductor device includes a substrate including a first region and a second region, memory transistors on the first region, a first interconnection layer on the memory transistors and including first interconnection lines, and a second interconnection layer on the first interconnection layer and including second interconnection lines. The second interconnection lines on the first region include a first line extending along a first direction and spaced from the second region by a first distance along the first direction, and a second line extending along the first direction, spaced from the first line along a second direction intersecting the first direction, and having a width smaller than that of the first line. The first line includes a protrusion extending along a third direction toward the substrate. The protrusion is spaced from the second region by a second distance along the first direction greater than the first distance.Type: GrantFiled: January 29, 2020Date of Patent: May 31, 2022Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Lakgyo Jeong, Seolun Yang, Yongrae Cho, Hee Bum Hong
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Publication number: 20220102364Abstract: Disclosed is a semiconductor memory device comprising a plurality of memory cells each including an access transistor, a pull-up transistor, and a pull-down transistor on a substrate, a first line layer on the memory cells and including a first lower landing pad and a second lower landing pad, a second line layer on the first line layer and including a ground line having an opening and an upper landing pad in the opening, and a third line layer including a word line on the second line layer. The ground line is electrically connected through the first lower landing pad to a terminal of the pull-down transistor. The word line is electrically connected through the upper landing pad and the second lower landing pad to a terminal of the access transistor.Type: ApplicationFiled: December 9, 2021Publication date: March 31, 2022Applicant: Samsung Electronics Co., Ltd.Inventors: Hee Bum HONG, Yongrae CHO
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Publication number: 20220077162Abstract: A semiconductor memory device includes a static random access memory (SRAM) cell that is provided on a substrate and includes a pass-gate transistor, a pull-down transistor, and a pull-up transistor. Each of the pass-gate transistor, the pull-down transistor, and the pull-up transistor includes an active fin protruding above a device isolation layer, a gate electrode on the active fin, and a gate insulating layer between the active fin and the gate electrode. The gate insulating layer of the pull-down transistor includes a first dipole element. The highest concentration of the first dipole element of the gate insulating layer of the pull-down transistor is higher than the highest concentration of the first dipole element of the gate insulating layer of the pass-gate transistor.Type: ApplicationFiled: March 8, 2021Publication date: March 10, 2022Inventors: HEE BUM HONG, HEESUNG SHIN, HOJOON LEE, YOUNGHUN JUNG, CHANG-MIN HONG
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Patent number: 11201160Abstract: Disclosed is a semiconductor memory device comprising a plurality of memory cells each including an access transistor, a pull-up transistor, and a pull-down transistor on a substrate, a first line layer on the memory cells and including a first lower landing pad and a second lower landing pad, a second line layer on the first line layer and including a ground line having an opening and an upper landing pad in the opening, and a third line layer including a word line on the second line layer. The ground line is electrically connected through the first lower landing pad to a terminal of the pull-down transistor. The word line is electrically connected through the upper landing pad and the second lower landing pad to a terminal of the access transistor.Type: GrantFiled: June 27, 2019Date of Patent: December 14, 2021Assignee: Samsung Electronics Co., Ltd.Inventors: Hee Bum Hong, Yongrae Cho
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Patent number: 10964707Abstract: A semiconductor device includes a substrate with a buffer region between first and second regions, the first region being a SRAM cell region, and the second region being a peripheral circuit region, first gate structures in a first direction on the first region and being spaced apart from each other in a second direction, second gate structures in the first direction on the second region and being spaced apart from each other in the second direction, the first and second gate structures being aligned with each other, a first insulating structure in the second direction on the buffer region between the first and the second regions along an entire length of each of the first and second regions in the second direction, and a second insulating structure on the first region and in contact with a part of the plurality of first gate structures.Type: GrantFiled: May 22, 2018Date of Patent: March 30, 2021Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Seol Un Yang, Lak Gyo Jeong, Hee Bum Hong
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Publication number: 20200168617Abstract: Disclosed is a semiconductor memory device comprising a plurality of memory cells each including an access transistor, a pull-up transistor, and a pull-down transistor on a substrate, a first line layer on the memory cells and including a first lower landing pad and a second lower landing pad, a second line layer on the first line layer and including a ground line having an opening and an upper landing pad in the opening, and a third line layer including a word line on the second line layer. The ground line is electrically connected through the first lower landing pad to a terminal of the pull-down transistor. The word line is electrically connected through the upper landing pad and the second lower landing pad to a terminal of the access transistor.Type: ApplicationFiled: June 27, 2019Publication date: May 28, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Hee Bum HONG, Yongrae Cho
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Publication number: 20200168596Abstract: A semiconductor device includes a substrate including a first region and a second region, memory transistors on the first region, a first interconnection layer on the memory transistors and including first interconnection lines, and a second interconnection layer on the first interconnection layer and including second interconnection lines. The second interconnection lines on the first region include a first line extending along a first direction and spaced from the second region by a first distance along the first direction, and a second line extending along the first direction, spaced from the first line along a second direction intersecting the first direction, and having a width smaller than that of the first line. The first line includes a protrusion extending along a third direction toward the substrate. The protrusion is spaced from the second region by a second distance along the first direction greater than the first distance.Type: ApplicationFiled: January 29, 2020Publication date: May 28, 2020Inventors: Lakgyo JEONG, Seolun YANG, Yongrae CHO, Hee Bum HONG
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Patent number: 10629582Abstract: A semiconductor device includes a substrate including a first region and a second region, memory transistors on the first region, a first interconnection layer on the memory transistors and including first interconnection lines, and a second interconnection layer on the first interconnection layer and including second interconnection lines. The second interconnection lines on the first region include a first line extending along a first direction and spaced from the second region by a first distance along the first direction, and a second line extending along the first direction, spaced from the first line along a second direction intersecting the first direction, and having a width smaller than that of the first line. The first line includes a protrusion extending along a third direction toward the substrate. The protrusion is spaced from the second region by a second distance along the first direction greater than the first distance.Type: GrantFiled: March 26, 2018Date of Patent: April 21, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Lakgyo Jeong, Seolun Yang, Yongrae Cho, Hee Bum Hong
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Patent number: 10387500Abstract: A semiconductor device includes a fin, first to fourth gate electrodes, first and second storage devices, first and second search terminals, and first and second dummy search terminals. The fin extend in a first direction. The gate electrodes intersecting the fin. The storage devices are connected with the gate electrodes. The first search terminal is connected with the second gate electrode and is spaced from the fin by a first distance. The second search terminal is connected with the third gate electrode and is spaced from the fin by a second distance different from the first distance. The first dummy search terminal is connected with the second gate electrode and is spaced from the fin by the second distance. The second dummy search terminal is connected with the third gate electrode and is spaced from the fin by the first distance.Type: GrantFiled: December 4, 2017Date of Patent: August 20, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hee Bum Hong, Chang Min Hong
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Publication number: 20190067265Abstract: A semiconductor device includes a substrate including a first region and a second region, memory transistors on the first region, a first interconnection layer on the memory transistors and including first interconnection lines, and a second interconnection layer on the first interconnection layer and including second interconnection lines. The second interconnection lines on the first region include a first line extending along a first direction and spaced from the second region by a first distance along the first direction, and a second line extending along the first direction, spaced from the first line along a second direction intersecting the first direction, and having a width smaller than that of the first line. The first line includes a protrusion extending along a third direction toward the substrate. The protrusion is spaced from the second region by a second distance along the first direction greater than the first distance.Type: ApplicationFiled: March 26, 2018Publication date: February 28, 2019Inventors: Lakgyo JEONG, Seolun YANG, Yongrae CHO, Hee Bum HONG
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Publication number: 20190067301Abstract: A semiconductor device includes a substrate with a buffer region between first and second regions, the first region being a SRAM cell region, and the second region being a peripheral circuit region, first gate structures in a first direction on the first region and being spaced apart from each other in a second direction, second gate structures in the first direction on the second region and being spaced apart from each other in the second direction, the first and second gate structures being aligned with each other, a first insulating structure in the second direction on the buffer region between the first and the second regions along an entire length of each of the first and second regions in the second direction, and a second insulating structure on the first region and in contact with a part of the plurality of first gate structures.Type: ApplicationFiled: May 22, 2018Publication date: February 28, 2019Inventors: Seol Un YANG, Lak Gyo JEONG, Hee Bum HONG
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Patent number: 10170472Abstract: A semiconductor device includes a substrate first through fourth active fins on the substrate, extending in a first direction, and spaced apart from one another in a second direction that intersects the first direction, a first gate electrode extending in the second direction and on the first active fin to overlap with the first active fin but not with the second through fourth active fins, a second gate electrode extending in the second direction and on the second and third active fins to overlap with the second active fin but not with the first and fourth active fins, a first contact on the first gate electrode and connected to a first wordline, and a second contact on the second gate electrode and connected to a second wordline. The first through third active fins are between the first and second contacts. Related devices are also discussed.Type: GrantFiled: June 26, 2017Date of Patent: January 1, 2019Assignee: Samsung Electronics Co., Ltd.Inventors: Lak Gyo Jeong, Yong Rae Cho, Kyo Wook Lee, Hee Bum Hong
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Publication number: 20180181679Abstract: A semiconductor device includes a fin, first to fourth gate electrodes, first and second storage devices, first and second search terminals, and first and second dummy search terminals. The fin extend in a first direction. The gate electrodes intersecting the fin. The storage devices are connected with the gate electrodes. The first search terminal is connected with the second gate electrode and is spaced from the fin by a first distance. The second search terminal is connected with the third gate electrode and is spaced from the fin by a second distance different from the first distance. The first dummy search terminal is connected with the second gate electrode and is spaced from the fin by the second distance. The second dummy search terminal is connected with the third gate electrode and is spaced from the fin by the first distance.Type: ApplicationFiled: December 4, 2017Publication date: June 28, 2018Inventors: Hee Bum Hong, Chang Min Hong
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Publication number: 20180040616Abstract: A semiconductor device includes a substrate first through fourth active fins on the substrate, extending in a first direction, and spaced apart from one another in a second direction that intersects the first direction, a first gate electrode extending in the second direction and on the first active fin to overlap with the first active fin but not with the second through fourth active fins, a second gate electrode extending in the second direction and on the second and third active fins to overlap with the second active fin but not with the first and fourth active fins, a first contact on the first gate electrode and connected to a first wordline, and a second contact on the second gate electrode and connected to a second wordline. The first through third active fins are between the first and second contacts. Related devices are also discussed.Type: ApplicationFiled: June 26, 2017Publication date: February 8, 2018Inventors: Lak Gyo Jeong, Yong Rae Cho, Kyo Wook Lee, Hee Bum Hong
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Patent number: 9780097Abstract: A dual-port SRAM device includes a substrate having a field region and first to fourth active fins extending in a first direction, and a unit cell having first to eighth gate structures. The first and second gate structures are on the first, second and fourth active fins, and extend in a second direction crossing the first direction. The third and fourth gate structures are on the first, second and third active fins, and extend in the second direction. The fifth and sixth gate structures are on the third active fin, and extend in the second direction. The seventh and eighth gate structures are on the fourth active fin, and extend in the second direction. The sixth gate structure is electrically connected to the third gate structure through the first contact plug, and the seventh gate structure is electrically connected to the second gate structure through a second contact plug.Type: GrantFiled: December 10, 2015Date of Patent: October 3, 2017Assignee: Samsung Electronics Co., Ltd.Inventors: Kyo-Wook Lee, Dong-Hun Lee, Hee-Bum Hong, Yong-Rae Cho
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Publication number: 20160190141Abstract: A dual-port SRAM device includes a substrate having a field region and first to fourth active fins extending in a first direction, and a unit cell having first to eighth gate structures. The first and second gate structures are on the first, second and fourth active fins, and extend in a second direction crossing the first direction. The third and fourth gate structures are on the first, second and third active fins, and extend in the second direction. The fifth and sixth gate structures are on the third active fin, and extend in the second direction. The seventh and eighth gate structures are on the fourth active fin, and extend in the second direction. The sixth gate structure is electrically connected to the third gate structure through the first contact plug, and the seventh gate structure is electrically connected to the second gate structure through a second contact plug.Type: ApplicationFiled: December 10, 2015Publication date: June 30, 2016Inventors: KYO-WOOK LEE, Dong-Hun Lee, Hee-Bum Hong, Yong-Rae Cho
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Publication number: 20160056161Abstract: A memory device including a substrate including a plurality of unit cell regions; a plurality of active regions on the substrate; and a plurality of gate electrodes on the substrate and extending in a first direction and intersecting at least one of the plurality of active regions, the plurality of active regions being adjacent to a boundary between the plurality of unit cell regions, and being separated from each other within the plurality of unit cell regions along a second direction orthogonal to the first direction.Type: ApplicationFiled: April 22, 2015Publication date: February 25, 2016Inventors: Hee Bum HONG, Lak GYO
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Publication number: 20110235407Abstract: A semiconductor memory device including a substrate, wherein the substrate includes first, second and third well regions, the first well region is disposed between the second and third well regions, the first well region includes a first type conductor and the second and third well regions each include a second type conductor.Type: ApplicationFiled: March 8, 2011Publication date: September 29, 2011Inventors: Sun-me Lim, Han-byung Park, Yong-shik Kim, Hee-bum Hong
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Patent number: 7638851Abstract: A semiconductor device in a peripheral circuit region includes a semiconductor substrate having a plurality of active areas which are disposed distantly from each other; a gate pattern including at least one gate disposed on the active area; a dummy gate disposed between the active areas and first and second pads; first and second pads connected to both sides of the gate and the dummy gate, respectively; and a first wiring formed so as to be in contact with at least one of the first and second pads.Type: GrantFiled: September 11, 2007Date of Patent: December 29, 2009Assignee: Hynix Semiconductor Inc.Inventors: Hee Bum Hong, Seong Taik Hong