Abstract: In a DRAM device having a capacitor and a method thereof, the capacitor included in the device is characterized to have a lower electrode that passes through a plurality of interlayer insulating layers. A first interlayer insulating layer is formed on a semiconductor substrate. A first contact plug layer is formed through the first interlayer insulating to electrically contact the semiconductor substrate. An insulating layer is formed on the first interlayer insulating layer. The insulating layer is etched to form the first interlayer insulating layer and a temporary storage node hole exposing the first contact plug. The first interlayer insulating layer exposed by the temporary storage node hole and portions of the first contact plug are simultaneously etched to form a storage node hole. A lower electrode layer is conformally formed on a surface of the semiconductor substrate having the storage node hole.

Abstract: A semiconductor device having a metal suicide layer and a method of manufacturing the same are provided. A spacer material layer is formed on a semiconductor substrate on which a gate and a source and drain region having a low impurity concentration are formed. Only the spacer material layer, which is formed in a region in which a silicide layer is to be formed, is etched. A source and drain region having a high impurity concentration is formed in the exposed semiconductor substrate, and a silicide layer is formed on the source and drain region having a high impurity concentration. Since an extra silicide blocking layer (SBL) is not formed, a photomask process of patterning a SBL is not performed. That is, one photolithographic process is reduced in comparison with a conventional process of selectively forming a silicide layer. Thus, a process of manufacturing a semiconductor device can be simplified, thereby reducing process costs and reducing the danger of misalignment occurring during a photomask process.