Abstract: A magnetic memory device and a method for fabricating the same are provided. The magnetic memory device includes a pinned layer pattern, a free layer pattern including boron (B), a tunnel barrier layer pattern between the pinned layer pattern and the free layer pattern, an oxide layer pattern spaced apart from the tunnel barrier layer pattern with the free layer pattern therebetween, the oxide layer pattern including a metal borate, and a capping layer pattern spaced apart from the free layer pattern with the oxide layer pattern therebetween, the capping layer pattern including a metal boride, wherein a difference between a boron concentration of the free layer pattern and a boron concentration of the oxide layer pattern is 10 at % or less, and a difference between the boron concentration of the oxide layer pattern and a boron concentration of the capping layer pattern is 10 at % or less.

Abstract: A magnetic memory device includes a pinned layer, a free layer, a tunnel barrier layer between the pinned layer and the free layer, a first oxide layer spaced apart from the tunnel barrier layer with the free layer therebetween, and a second oxide layer spaced apart from the free layer with the first oxide layer therebetween. The first oxide layer includes an oxide of a first material and may have a thickness of 0.3 ? to 2.0 ?. The second oxide layer may include an oxide of a second material and may have a thickness of 0.1 ? to 5.0 ?. A first oxygen affinity of the first material may be greater than a second oxygen affinity of the second material.

Abstract: A sputtering apparatus including a chamber, a stage inside the chamber and configured to receive a substrate thereon, a first sputter gun configured to provide a sputtering source to an inside of the chamber, a first RF source configured to provide a first power having a first frequency to the first sputter gun, and a second RF source configured to provide a second power having a second frequency to the first sputter gun, the second frequency being lower than the first frequency may be provided.

Abstract: An image sensor is provided. The image sensor includes unit pixels inside the substrate; a pixel separation pattern provided between the unit pixels, inside the substrate; a first inter-wiring insulating film provided on the first surface of the substrate; a pad pattern provided inside the first inter-wiring insulating film; a first connection pattern provided inside the first inter-wiring insulating film, an upper surface of the first connection pattern and an upper surface of the first inter-wiring insulating film being provided along a first common plane; a second inter-wiring insulating film provided on the upper surface of the first inter-wiring insulating film; a second connection pattern provided inside the second inter-wiring insulating film, a lower surface of the second connection pattern and a lower surface of the second inter-wiring insulating film being provided along a second common plane; and a microlens provided on the second surface of the substrate.

Abstract: A sputtering apparatus including a chamber, a stage inside the chamber and configured to receive a substrate thereon, a first sputter gun configured to provide a sputtering source to an inside of the chamber, a first RF source configured to provide a first power having a first frequency to the first sputter gun, and a second RF source configured to provide a second power having a second frequency to the first sputter gun, the second frequency being lower than the first frequency may be provided.

Abstract: A sputtering apparatus including a chamber, a stage inside the chamber and configured to receive a substrate thereon, a first sputter gun configured to provide a sputtering source to an inside of the chamber, a first RF source configured to provide a first power having a first frequency to the first sputter gun, and a second RF source configured to provide a second power having a second frequency to the first sputter gun, the second frequency being lower than the first frequency may be provided.

Abstract: A magnetic memory device includes a pinned layer, a free layer, a tunnel barrier layer between the pinned layer and the free layer, a first oxide layer spaced apart from the tunnel barrier layer with the free layer therebetween, and a second oxide layer spaced apart from the free layer with the first oxide layer therebetween. The first oxide layer includes an oxide of a first material and may have a thickness of 0.3 ? to 2.0 ?. The second oxide layer may include an oxide of a second material and may have a thickness of 0.1 ? to 5.0 ?. A first oxygen affinity of the first material may be greater than a second oxygen affinity of the second material.

Abstract: A semiconductor device includes a storage layer including at least one first magnetic layer and a reference layer facing the storage layer and including at least one second magnetic layer. The device also includes a tunnel barrier layer between the storage layer and the reference layer. The device further includes at least one spin-orbit torque line adjacent the storage layer.

Abstract: An MRAM device includes a first conductive pattern including a material generating a spin orbital torque, a torque transfer pattern contacting a portion of an upper surface of the first conductive pattern, an insulation pattern on a side of the torque transfer pattern and covering the first conductive pattern, and a magnetic tunnel junction (MTJ) structure on the torque transfer pattern, the MTJ structure including a free layer pattern, a tunnel barrier pattern, and a fixed layer pattern sequentially stacked.

Abstract: A semiconductor device includes a storage layer including at least one first magnetic layer and a reference layer facing the storage layer and including at least one second magnetic layer. The device also includes a tunnel barrier layer between the storage layer and the reference layer. The device further includes at least one spin-orbit torque line adjacent the storage layer.

Abstract: A sputtering apparatus including a chamber, a stage inside the chamber and configured to receive a substrate thereon, a first sputter gun configured to provide a sputtering source to an inside of the chamber, a first RF source configured to provide a first power having a first frequency to the first sputter gun, and a second RF source configured to provide a second power having a second frequency to the first sputter gun, the second frequency being lower than the first frequency may be provided.

Abstract: A semiconductor device includes a storage layer including at least one first magnetic layer and a reference layer facing the storage layer and including at least one second magnetic layer. The device also includes a tunnel barrier layer between the storage layer and the reference layer. The device further includes at least one spin-orbit torque line adjacent the storage layer.

Abstract: An MRAM device includes a first conductive pattern including a material generating a spin orbital torque, a torque transfer pattern contacting a portion of an upper surface of the first conductive pattern, an insulation pattern on a side of the torque transfer pattern and covering the first conductive pattern, and a magnetic tunnel junction (MTJ) structure on the torque transfer pattern, the MTJ structure including a free layer pattern, a tunnel barrier pattern, and a fixed layer pattern sequentially stacked.

Abstract: A semiconductor device includes a storage layer including at least one first magnetic layer and a reference layer facing the storage layer and including at least one second magnetic layer. The device also includes a tunnel barrier layer between the storage layer and the reference layer. The device further includes at least one spin-orbit torque line adjacent the storage layer.

Abstract: There is provided a non-volatile memory device which can enhance the reliability of a memory device by using an ovonic threshold switch (OTS) selection element including a multilayer structure. The non-volatile memory device includes a first electrode and a second electrode spaced apart from each other, a selection element layer between the first electrode and the second electrode, which is closer to the second electrode rather than to the first electrode, and which includes a first chalcogenide layer, a second chalcogenide layer, and a material layer disposed between the first and second chalcogenide layers. The first chalcogenide layer including a first chalcogenide material, and the second chalcogenide layer including a second chalcogenide material. A memory layer between the first electrode and the selection element layer includes a third chalcogenide material which is different from the first and second chalcogenide materials.

Abstract: There is provided a non-volatile memory device which can enhance the reliability of a memory device by using an ovonic threshold switch (OTS) selection element including a multilayer structure. The non-volatile memory device includes a first electrode and a second electrode spaced apart from each other, a selection element layer between the first electrode and the second electrode, which is closer to the second electrode rather than to the first electrode, and which includes a first chalcogenide layer, a second chalcogenide layer, and a material layer disposed between the first and second chalcogenide layers. The first chalcogenide layer including a first chalcogenide material, and the second chalcogenide layer including a second chalcogenide material. A memory layer between the first electrode and the selection element layer includes a third chalcogenide material which is different from the first and second chalcogenide materials.

Abstract: A semiconductor device is provided having a free layer and a pinned layer spaced apart from each other. A tunnel barrier layer is formed between the free layer and the pinned layer. The pinned layer may include a lower pinned layer, and an upper pinned layer spaced apart from the lower pinned layer. A spacer may be formed between the lower pinned layer and the upper pinned layer. A non-magnetic junction layer may be disposed adjacent to the spacer or between layers in the upper or lower pinned layer.

Abstract: A magnetic device can include a tunnel bather and a hybrid magnetization layer disposed adjacent the tunnel barrier. The hybrid magnetization layer can include a first perpendicular magnetic anisotropy (PMA) layer, a second PMA layer, and an amorphous blocking layer disposed between the first and second PMA layers. The first PMA layer can include a multi-layer film in which a first layer formed of Co and a second layer formed of Pt or Pd are alternately stacked. A first dopant formed of an element different from those of the first and second layers can also be included in the first PMA layer. The second PMA layer can be disposed between the first PMA layer and the tunnel barrier, and can include at least one element selected from a group consisting of Co, Fe, and Ni.

Abstract: A semiconductor device is provided having a free layer and a pinned layer spaced apart from each other. A tunnel barrier layer is formed between the free layer and the pinned layer. The pinned layer may include a lower pinned layer, and an upper pinned layer spaced apart from the lower pinned layer. A spacer may be formed between the lower pinned layer and the upper pinned layer. A non-magnetic junction layer may be disposed adjacent to the spacer or between layers in the upper or lower pinned layer.

Abstract: A semiconductor device is provided having a free layer and a pinned layer spaced apart from each other. A tunnel barrier layer is formed between the free layer and the pinned layer. The pinned layer may include a lower pinned layer, and an upper pinned layer spaced apart from the lower pinned layer. A spacer may be formed between the lower pinned layer and the upper pinned layer. A non-magnetic junction layer may be disposed adjacent to the spacer or between layers in the upper or lower pinned layer.