Abstract: A semiconductor device and a method for manufacturing the same are disclosed, which can form a gate electrode material only in a recess of a buried gate cell structure, improve a Gate Induced Drain Leakage (GIDL) of a gate electrode material and a junction (i.e., drain region), prevent the gate electrode material from overlapping with the junction (i.e., drain region), and adjust the depth of junction, thereby improving channel resistance. The method for manufacturing a semiconductor device includes forming a device isolation region defining an active region over a semiconductor substrate, burying a gate electrode material in the semiconductor substrate, forming a gate electrode pattern by etching the gate electrode material, wherein the gate electrode pattern is formed at sidewalls of the active region including a source region, and forming a capping layer in the exposed active region.

Abstract: An array substrate including: a gate barrier layer on a substrate; a gate line on the gate barrier layer, the gate line having a gate open portion exposing the gate barrier layer in a gate electrode region; a gate insulating layer on the gate line; an active layer on the gate insulating layer over the gate barrier layer in the gate electrode region; and source and drain electrodes spaced apart from each other on the active layer.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed, which can form a gate electrode material only in a recess of a buried gate cell structure, improve a Gate Induced Drain Leakage (GIDL) of a gate electrode material and a junction (i.e., drain region), prevent the gate electrode material from overlapping with the junction (i.e., drain region), and adjust the depth of junction, thereby improving channel resistance. The method for manufacturing a semiconductor device includes forming a device isolation region defining an active region over a semiconductor substrate, burying a gate electrode material in the semiconductor substrate, forming a gate electrode pattern by etching the gate electrode material, wherein the gate electrode pattern is formed at sidewalls of the active region including a source region, and forming a capping layer in the exposed active region.

Abstract: An oxide thin film transistor (TFT) includes an oxide semiconductor layer including a first semiconductor layer and a second semiconductor layer on the first semiconductor layer; a gate insulating layer on the oxide semiconductor layer; a gate electrode on the gate insulating layer; an interlayer insulating layer on the gate electrode; and a source electrode and a drain electrode on the interlayer insulating layer and contacting the oxide semiconductor layer, wherein a first reflectance of the first semiconductor layer is greater than a second semiconductor layer.

Abstract: An array substrate including: a gate barrier layer on a substrate; a gate line on the gate barrier layer, the gate line having a gate open portion exposing the gate barrier layer in a gate electrode region; a gate insulating layer on the gate line; an active layer on the gate insulating layer over the gate barrier layer in the gate electrode region; and source and drain electrodes spaced apart from each other on the active layer.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed, which can form a gate electrode material only in a recess of a buried gate cell structure, improve a Gate Induced Drain Leakage (GIDL) of a gate electrode material and a junction (i.e., drain region), prevent the gate electrode material from overlapping with the junction (i.e., drain region), and adjust the depth of junction, thereby improving channel resistance. The method for manufacturing a semiconductor device includes forming a device isolation region defining an active region over a semiconductor substrate, burying a gate electrode material in the semiconductor substrate, forming a gate electrode pattern by etching the gate electrode material, wherein the gate electrode pattern is formed at sidewalls of the active region including a source region, and forming a capping layer in the exposed active region.

Abstract: A low-resistance wiring structure and a liquid crystal display are disclosed. The liquid crystal display includes a first substrate; a thin film transistor (TFT) formed on the first substrate and formed of a gate wiring, a data wiring and a semiconductor layer; and a second substrate attached to the first substrate in a facing manner, wherein at least one of the gate wiring and the data wiring is formed as a first wiring made of copper, a second wiring made of a barrier metal preventing spreading of copper, and a metal oxide film pattern formed between the first and second wirings. A MO/Cu wiring structure is implemented by using pure molybdenum, so that the low-resistance wiring structure with high reliability can be formed at a low cost.

Abstract: A method of fabrication an array substrate includes forming an oxide semiconductor layer on a substrate; sequentially forming a gate insulating layer and a gate electrode corresponding to a central portion of the oxide semiconductor layer; forming source and drain areas having conductive properties in the oxide semiconductor layer by performing hydrogen plasma treatment; forming barrier layers on the source and drain areas, the barrier layer having a first thickness; forming an inter insulating layer on the gate electrode and having first contact holes that expose the barrier layers; and forming source and drain electrodes on the inter insulating layer and contacting the barrier layers through the first contact holes, respectively.

Abstract: The present invention relates to a semiconductor device, which includes a junction region formed in an active area of a semiconductor substrate; a trench defining a buried gate predetermined area within the semiconductor substrate; a gate electrode buried in an lower portion of the trench; an ion implantation region formed in a sidewall of the trench; and a capping insulation layer formed in an upper portion of the gate electrode.

Abstract: A semiconductor memory device has an asymmetric buried gate structure with a stepped top surface and a method for fabricating the same. The method for fabricating the semiconductor memory device includes: etching a predetermined region of a semiconductor substrate to form an isolation layer defining an active region; forming a recess within the active region; forming a metal layer filling the recess; asymmetrically etching the metal layer to form an asymmetric gate having a stepped top surface at a predetermined portion of the recess; and forming a capping oxide layer filling a remaining portion of the recess where the asymmetric gate is not formed, thereby obtaining an asymmetric buried gate including the asymmetric gate and the capping oxide layer.

Abstract: Disclosed is an LCD device comprising: a substrate; gate and data lines intersecting each other on the substrate; a thin film transistor at the intersection of the gate and data lines; a pixel electrode electrically connected with the thin film transistor; a common electrode forming an electric field with the pixel electrode; and a reflection control layer on at least one of the pixel electrode and common electrode. At this time, at least one electrode of the pixel electrode and common electrode is formed of the opaque metal material, to thereby improve black luminance and contrast ratio. Simultaneously, the reflection control layer is formed on the at least one electrode of the opaque metal material so that it is possible to adjust the reflectivity of external light, and to prevent the problem of rainbow-colored image.

Abstract: The present invention relates to a semiconductor device, which includes a junction region formed in an active area of a semiconductor substrate; a trench defining a buried gate predetermined area within the semiconductor substrate; a gate electrode buried in an lower portion of the trench; an ion implantation region formed in a sidewall of the trench; and a capping insulation layer formed in an upper portion of the gate electrode.

Abstract: The present invention relates to a semiconductor device, which includes a junction region formed in an active area of a semiconductor substrate; a trench defining a buried gate predetermined area within the semiconductor substrate; a gate electrode buried in an lower portion of the trench; an ion implantation region formed in a sidewall of the trench; and a capping insulation layer formed in an upper portion of the gate electrode.

Abstract: A semiconductor device includes a first plug formed on a semiconductor substrate and exposed on side and upper surfaces of an upper part thereof and a second plug formed on the first plug to contact the exposed side and upper surfaces of the upper part of the first plug.

Abstract: A semiconductor device and a method for manufacturing the same are disclosed, which can form a gate electrode material only in a recess of a buried gate cell structure, improve a Gate Induced Drain Leakage (GIDL) of a gate electrode material and a junction (i.e., drain region), prevent the gate electrode material from overlapping with the junction (i.e., drain region), and adjust the depth of junction, thereby improving channel resistance. The method for manufacturing a semiconductor device includes forming a device isolation region defining an active region over a semiconductor substrate, burying a gate electrode material in the semiconductor substrate, forming a gate electrode pattern by etching the gate electrode material, wherein the gate electrode pattern is formed at sidewalls of the active region including a source region, and forming a capping layer in the exposed active region.

Abstract: The present invention relates to a copper wire in a semiconductor device in which a barrier layer is formed for improving adhesion of a copper wire without any additional fabricating step; a method for fabricating the same, and a flat panel display device with the same. The copper wire includes a barrier layer formed on an underlying structure, and a copper conductive layer on the barrier layer, wherein the barrier layer includes at least one of a Cu2O layer and a CuOxNy layer.

Abstract: A semiconductor device includes a first plug formed on a semiconductor substrate and exposed on side and upper surfaces of an upper part thereof and a second plug formed on the first plug to contact the exposed side and upper surfaces of the upper part of the first plug.

Abstract: Disclosed is an LCD device comprising: a substrate; gate and data lines intersecting each other on the substrate; a thin film transistor at the intersection of the gate and data lines; a pixel electrode electrically connected with the thin film transistor; a common electrode forming an electric field with the pixel electrode; and a reflection control layer on at least one of the pixel electrode and common electrode. At this time, at least one electrode of the pixel electrode and common electrode is formed of the opaque metal material, to thereby improve black luminance and contrast ratio. Simultaneously, the reflection control layer is formed on the at least one electrode of the opaque metal material so that it is possible to adjust the reflectivity of external light, and to prevent the problem of rainbow-colored image.

Abstract: A semiconductor device includes a first plug formed on a semiconductor substrate and exposed on side and upper surfaces of an upper part thereof and a second plug formed on the first plug to contact the exposed side and upper surfaces of the upper part of the first plug.

Abstract: A liquid crystal display (LCD) device having an array substrate with a top gate type TFT includes a first transparent metal layer deposited to enhance the adhesion between a data metal layer and an insulating substrate before a data metal deposition, and a second transparent metal layer deposited to enhance the adhesion between a gate metal layer and an insulating substrate before a gate metal deposition. The LCD device having the array substrate with a top gate type TFT can be fabricated with a reduced number of masking or sputtering processes, thereby reducing the fabrication time of the LCD device and increasing the yield of the LCD device.