Abstract: A semiconductor integrated circuit including a plurality of cores and/or a plurality of user defined logic (UDL) circuits, also includes a scan signal converting circuit to generate a plurality of scan signals to test the cores and/or the circuits adopting various scan styles in core-based design. The scan signal converting circuit converts scan signals corresponding one of the scan styles into various scan signals to control shift and normal operation of the embedded plural cores and/or the UDL circuits. As a result, the integrated circuit having a plurality of cores and/or the UDL circuits can be tested by the generated various scan signals from the scan signal converting circuit, under control of the scan signals corresponding to one of the scan styles. Therefore, the integrated circuit can easily perform test algorithms such as automatic test-pattern generation (ATPG) algorithm, and the like.

Abstract: A semiconductor integrated circuit including a plurality of cores and/or a plurality of user defined logic (UDL) circuits, also includes a scan signal converting circuit to generate a plurality of scan signals to test the cores and/or the circuits adopting various scan styles in core-based design. The scan signal converting circuit converts scan signals corresponding one of the scan styles into various scan signals to control shift and normal operation of the embedded plural cores and/or the UDL circuits. As a result, the integrated circuit having a plurality of cores and/or the UDL circuits can be tested by the generated various scan signals from the scan signal converting circuit, under control of the scan signals corresponding to one of the scan styles. Therefore, the integrated circuit can easily perform test algorithms such as automatic test-pattern generation (ATPG) algorithm, and the like.