Abstract: A spot compensating apparatus including a spot compensation data generator configured to generate spot compensation data based on a first precision unit in a first block area having a spot, and based on a second precision unit in a second block area not having the spot, the spot compensation data being for compensating the spot displayed on a display panel configured to display an image based on first image data, the second precision unit having less precision than the first precision unit, and a spot compensator configured to perform a spot compensation on the first image data using the spot compensation data to output second image data.

Abstract: An afterimage compensator and a display device having the same are disclosed, and the afterimage compensator includes an image analyzer configured to determine an amount of image variation based on a change of image data, and an image shifter configured to adjust a shift interval, which is an interval between time points at which an image is shifted, according to the amount of image variation.

Abstract: In a method of manufacturing a vertical memory device, a first sacrificial layer including a nitride is formed on a substrate. A mold including an insulation layer and a second sacrificial layer alternately and repeatedly stacked on the first sacrificial layer is formed. The insulation layer and the second sacrificial layer include a first oxide and a second oxide, respectively. A channel is formed through the mold and the first sacrificial layer. An opening is formed through the mold and the first sacrificial layer to expose an upper surface of the substrate. The first sacrificial layer is removed through the opening to form a first gap. A channel connecting pattern is formed to fill the first gap. The second sacrificial layer is replaced with a gate electrode.

Abstract: A fan-out semiconductor package includes: a core member including a support layer, a first wiring layer, a second wiring layer, and through-vias and having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant covering the core member and the semiconductor chip and filling at least portions of the through-hole; a connection member including an insulating layer disposed on the first wiring layer and the semiconductor chip, a redistribution layer disposed on the insulating layer, first vias electrically connecting the redistribution layer and the connection pads to each other, and second vias electrically connecting the redistribution layer and the first wiring layer to each other; and a passivation layer disposed on the insulating layer and covering the redistribution layer, wherein a thickness of the passivation layer is within half a distance from an inactive surface of the semiconductor chip to a lower surface of the encapsulant.

Abstract: A method of manufacturing a semiconductor device, the method including supplying a first reactant to inside a processing chamber into which a substrate has been introduced; controlling a flow of a first purge gas and storing the first purge gas, of which flow has been controlled, in a first storage for a given time period; supplying the first purge gas from the first storage to the inside of the processing chamber after supplying the first reactant; and supplying a second reactant to the inside of the processing chamber after supplying the first purge gas.

Abstract: A fan-out semiconductor package includes: a core member including a support layer, a first wiring layer, a second wiring layer, and through-vias and having a through-hole; a semiconductor chip disposed in the through-hole; an encapsulant covering the core member and the semiconductor chip and filling at least portions of the through-hole; a connection member including an insulating layer disposed on the first wiring layer and the semiconductor chip, a redistribution layer disposed on the insulating layer, first vias electrically connecting the redistribution layer and the connection pads to each other, and second vias electrically connecting the redistribution layer and the first wiring layer to each other; and a passivation layer disposed on the insulating layer and covering the redistribution layer, wherein a thickness of the passivation layer is within half a distance from an inactive surface of the semiconductor chip to a lower surface of the encapsulant.

Abstract: An organic light emitting display device includes: a display panel including a plurality of pixels; a controller configured to correct input image signals supplied from the outside according to an amount of voltage drop; a data driver configured to supply data signals corresponding to the corrected image signals; and a scan driver configured to supply scan signals to scan lines. The controller includes: a load factor calculator configured to calculate a load factor of a panel; a horizontal block load factor calculator configured to calculate a driving current of a plurality of horizontal blocks formed by dividing the panel according to the scan lines; a voltage drop amount calculator configured to calculate the amount of the voltage drop based on the driving current; and a lookup table generator configured to generate a voltage drop correction lookup table based on the amount of the voltage drop.

Abstract: A Semiconductor device and method for fabricating the same are provided. The method includes forming a trench in a substrate, forming a lower gate metal using a first gas, the lower gate metal burying at least a portion of the trench, forming a barrier metal on the lower gate metal, on the barrier metal, forming an upper gate metal using a second gas different from the first gas and forming a capping film on the gate metal, the capping film filling the trench.

Abstract: A Semiconductor device and method for fabricating the same are provided. The method includes forming a trench in a substrate, forming a lower gate metal using a first gas, the lower gate metal burying at least a portion of the trench, forming a barrier metal on the lower gate metal, on the barrier metal, forming an upper gate metal using a second gas different from the first gas and forming a capping film on the gate metal, the capping film filling the trench.

Abstract: A method of fabricating a semiconductor device includes forming a doped polysilicon layer on a substrate, forming a barrier layer on the doped polysilicon layer, forming an oxidized barrier layer by oxidizing a surface of the barrier layer, and forming a metal layer on the oxidized barrier layer.

Abstract: A method of manufacturing a semiconductor device, the method including supplying a first reactant to inside a processing chamber into which a substrate has been introduced; controlling a flow of a first purge gas and storing the first purge gas, of which flow has been controlled, in a first storage for a given time period; supplying the first purge gas from the first storage to the inside of the processing chamber after supplying the first reactant; and supplying a second reactant to the inside of the processing chamber after supplying the first purge gas.

Abstract: A method of forming a tungsten film including disposing a substrate inside a process chamber; performing a tungsten nucleation layer forming operation for forming a tungsten nucleation layer on the substrate, performing a first operation for forming a portion of a tungsten bulk layer on the tungsten nucleation layer by alternately supplying a tungsten-containing gas and a reducing gas into the process chamber, and performing a second operation for stopping the supply of the tungsten-containing gas and the reducing gas and removing a remaining gas in the process chamber may be provided. The first operation and the second operation may be repeated at least twice until the tungsten bulk layer reaches a desired thickness.

Abstract: A spot compensating apparatus including a spot compensation data generator configured to generate spot compensation data based on a first precision unit in a first block area having a spot, and based on a second precision unit in a second block area not having the spot, the spot compensation data being for compensating the spot displayed on a display panel configured to display an image based on first image data, the second precision unit having less precision than the first precision unit, and a spot compensator configured to perform a spot compensation on the first image data using the spot compensation data to output second image data.

Abstract: A method of fabricating a semiconductor device includes forming a doped polysilicon layer on a substrate, forming a barrier layer on the doped polysilicon layer, forming an oxidized barrier layer by oxidizing a surface of the barrier layer, and forming a metal layer on the oxidized barrier layer.

Abstract: Semiconductor devices, and methods for fabricating a semiconductor device, include forming a contact hole penetrating an interlayer insulating layer and exposing a conductor defining a bottom surface of the contact hole, forming a sacrificial layer filling the contact hole, forming a first trench overlapping a part of the contact hole by removing at least a part of the sacrificial layer, forming a spacer filling the first trench, forming a second trench by removing a remainder of the sacrificial layer, and forming a metal electrode filling the contact hole and the second trench using electroless plating.

Abstract: Semiconductor devices, and methods for fabricating a semiconductor device, include forming a contact hole penetrating an interlayer insulating layer and exposing a conductor defining a bottom surface of the contact hole, forming a sacrificial layer filling the contact hole, forming a first trench overlapping a part of the contact hole by removing at least a part of the sacrificial layer, forming a spacer filling the first trench, forming a second trench by removing a remainder of the sacrificial layer, and forming a metal electrode filling the contact hole and the second trench using electroless plating.

Abstract: A semiconductor device includes a gate trench across an active region of a semiconductor substrate, a gate structure filling the gate trench, and source/drain regions formed in the active region at respective sides of the gate structure. The gate structure includes a sequentially stacked gate electrode and insulating capping pattern, and a gate dielectric layer between the gate electrode and the active region. The gate electrode is located at a lower level than an upper surface of the active region and includes a barrier conductive pattern and a gate conductive pattern. The gate conductive pattern includes a first part having a first width and a second part having a second width greater than the first width. The barrier conductive pattern is interposed between the first part of the gate conductive pattern and the gate dielectric layer.

Abstract: An organic light emitting display device includes: a display panel including a plurality of pixels; a controller configured to correct input image signals supplied from the outside according to an amount of voltage drop; a data driver configured to supply data signals corresponding to the corrected image signals; and a scan driver configured to supply scan signals to scan lines. The controller includes: a load factor calculator configured to calculate a load factor of a panel; a horizontal block load factor calculator configured to calculate a driving current of a plurality of horizontal blocks formed by dividing the panel according to the scan lines; a voltage drop amount calculator configured to calculate the amount of the voltage drop based on the driving current; and a lookup table generator configured to generate a voltage drop correction lookup table based on the amount of the voltage drop.

Abstract: A semiconductor device includes: a semiconductor substrate having a trench therein, a metal-containing barrier layer extending along an inner wall of the trench and defining a wiring space in the trench, the wiring space having a first width along a first direction, and a metal-containing conductive line on the metal-containing barrier layer in the wiring space, and including at least one metal grain having a particle diameter of about the first width along the first direction.

Abstract: A semiconductor device includes a gate trench across an active region of a semiconductor substrate, a gate structure filling the gate trench, and source/drain regions formed in the active region at respective sides of the gate structure. The gate structure includes a sequentially stacked gate electrode and insulating capping pattern, and a gate dielectric layer between the gate electrode and the active region. The gate electrode is located at a lower level than an upper surface of the active region and includes a barrier conductive pattern and a gate conductive pattern. The gate conductive pattern includes a first part having a first width and a second part having a second width greater than the first width. The barrier conductive pattern is interposed between the first part of the gate conductive pattern and the gate dielectric layer.