Abstract: A metal contact in a semiconductor device is formed by forming an insulating layer having a contact hole therein on a silicon substrate. A cobalt layer is formed on a bottom and inner walls of the contact hole. A cobalt silicide layer is formed at the bottom of the contact hole while forming a titanium layer on the cobalt layer. A plug is formed on the titanium layer so as to fill the contact hole.

Abstract: An integrated circuit of a semiconductor device has a line type of pattern that is not prone to serious RC delays. The integrated circuit has a line formed of at least a layer of polycrystalline silicon, a layer of metal having a low sheet resistance, and a layer of a barrier metal interposed between the polycrystalline silicon and the metal having a low sheet resistance, and first spacers disposed on the sides of the line, respectively, and is characterized in that the line has recesses at the sides of the barrier layer and the first spacers fill the recesses. The integrated circuit may constitute a gate line of a semiconductor device. The integrated circuit is formed by forming layers of polycrystalline silicon, metal having a low sheet resistance, and a barrier metal one atop the other, patterning the layers into a line, etching the same to form the recesses, and then forming the first spacers.

Abstract: A method of forming a tungsten silicide layer and a related method of fabricating a semiconductor element. The method of forming the tungsten silicide layer includes forming a pre-coating layer within a CVD process chamber by injecting a tungsten source gas (A) and a silicon source gas (B) at a flow ratio (A/B) of 1/50 or less, and thereafter loading a semiconductor substrate into the CVD process chamber in which the precoating layer is formed, and injecting additional tungsten source gas and silicon source gas to form the tungsten silicide layer on the semiconductor substrate.

Abstract: Example embodiments relate to a multilayer gate electrode, a semiconductor device having the same and methods of fabricating the same. Other example embodiments relate to a semiconductor device with a multilayer gate electrode which is relatively stable at higher temperatures, has improved resistance characteristics and improved reliability, and methods of fabricating the same. The multilayer gate electrode may include a polycrystalline semiconductor layer on the gate insulating layer and doped with conductive type impurities, an ohmic contact layer on the polycrystalline semiconductor layer and including tungsten (W1?x) and non-tungsten metal (Mx, x=about 0.01 to about 0.55), a metal barrier layer on the ohmic contact layer and a refractory metal layer on the metal barrier layer.

Abstract: Semiconductor devices and methods of fabricating the same are provided. A gate insulating film is provided on a semiconductor substrate. A polymetal gate electrode is provided on the gate insulating film. The polymetal gate electrode includes a conductive polysilicon film on the gate insulating film, a first metal silicide film on the conductive polysilicon film, a barrier film on the first metal silicide film, and a metal film on the barrier film. The barrier film includes a titanium nitride (TiN) film on the first metal silicide film and a buffer layer between the TiN film and the metal film.

Abstract: In one embodiment, a semiconductor device comprises a semiconductor substrate and a doped conductive layer formed over the semiconductor substrate. A diffusion barrier layer is formed over the doped conductive layer. The diffusion barrier layer comprises an amorphous semiconductor material. An ohmic contact layer is formed over the diffusion barrier layer. A metal barrier layer is formed over the ohmic contact layer. A metal layer is formed over the metal barrier layer.

Abstract: In one embodiment, a semiconductor device comprises a semiconductor substrate and a doped conductive layer formed over the semiconductor substrate. A diffusion barrier layer is formed over the doped conductive layer. The diffusion barrier layer comprises an amorphous semiconductor material. After forming the diffusion barrier layer, a heat treatment process may be additionally performed thereon. An ohmic contact layer is formed over the diffusion barrier layer. A metal barrier layer is formed over the ohmic contact layer. A metal layer is formed over the metal barrier layer.

Abstract: An integrated circuit device, e.g., a memory device, includes a substrate, a first insulation layer on the substrate, and a contact pad disposed in the first insulation layer in direct contact with the substrate. A second insulation layer is disposed on the first insulation layer. A conductive pattern, e.g., a damascene bit line, is disposed in the second insulation layer. A conductive plug extends through the second insulation layer to contact the contact pad and is self-aligned to the conductive pattern. An insulation film may separate the conductive pattern and the conductive plug. A glue layer may be disposed between the conductive pattern and the second insulation layer. The device may further include a third insulation layer on the second insulation layer and the conductive pattern, and the conductive plug may extend through the second and third insulation layers.

Abstract: Methods of forming semiconductor devices and the devices so formed include forming an oxidation barrier pattern to cover sidewalls of a metal-containing pattern. The metal-containing pattern is located on a gate polysilicon layer and includes a metal silicide pattern, a metal barrier pattern and a gate metal pattern which are sequentially stacked. An oxide layer is not formed between the metal barrier pattern and the gate polysilicon pattern. Furthermore, a metal silicide pattern located between the metal barrier pattern and the gate polysilicon pattern functions not only as an ohmic layer decreasing a contact resistance between the metal barrier pattern and the gate polysilicon pattern but also as an oxidation barrier to prevent a metal such as tungsten from being oxidized. Therefore, semiconductor devices have improved operational speed and/or reliability.

Abstract: In an ohmic layer and methods of forming the ohmic layer, a gate structure including the ohmic layer and a metal wiring having the ohmic layer, the ohmic layer is formed using tungsten silicide that includes tungsten and silicon with an atomic ratio within a range of about 1:5 to about 1:15. The tungsten silicide may be obtained in a chamber using a reaction gas including a tungsten source gas and a silicon source gas by a partial pressure ratio within a range of about 1.0:25.0 to about 1.0:160.0. The reaction gas may have a partial pressure within a range of about 2.05 percent to about 30.0 percent of a total internal pressure of the chamber. When the ohmic layer is employed for a conductive structure, such as a gate structure or a metal wiring, the conductive structure may have a reduced resistance.

Abstract: A method for forming a contact of a semiconductor device is disclosed. A first interlevel dielectric (ILD) layer is formed on a conductive region, e.g., an active region. The first ILD layer is etched to form a first contact hole therein to expose the conductive region. The first contact hole is filled with a porous layer having a high etch selectivity with respect to the first ILD layer to form a porous plug therein. Next, a second ILD layer is formed overlying the porous plug. The second ILD layer is etched to form a second contact hole therein to expose the porous plug. The porous plug in the first contact hole is removed. The first and second contact holes are filled with a conductive material to form a contact plug. During this contact formation process, the active region or the conductive region of the semiconductor substrate can be protected with the porous plug.

Abstract: A contact hole can be formed in an insulating layer to expose a surface of an underlying silicon layer at a bottom of the contact hole having a first size. A metal silicide layer can be formed beneath the bottom of the contact hole and removed to form a void beneath the contact hole having a second size that is greater than the first size.

Abstract: In a method of manufacturing a semiconductor device including a polysilicon layer on which a heat treatment is performed in hydrogen atmosphere, a preliminary polysilicon layer is formed on a semiconductor substrate. Fluorine (F) impurities are implanted onto the preliminary polysilicon layer, so that the preliminary polysilicon layer is formed into a polysilicon layer. A main heat treatment is performed on the polysilicon layer, thereby preventing a void caused by the fluorine (F) in the polysilicon layer. A subsidiary heat treatment is further performed on the polysilicon layer prior to the main heat treatment, thereby activating dopants in the polysilicon layer. Electrical characteristics and performance of a semiconductor device are improved since the void is sufficiently prevented in the polysilicon layer.

Abstract: In a method for forming a gate in a semiconductor device, a first preliminary gate structure is formed on a substrate. The first preliminary gate structure includes a gate oxide layer, a polysilicon layer pattern and a tungsten layer pattern sequentially stacked on the substrate. A primary oxidation process is performed using oxygen radicals at a first temperature for adjusting a thickness of the gate oxide layer to form a second preliminary gate structure having tungsten oxide. The tungsten oxide is reduced to a tungsten material using a gas containing hydrogen to form a gate structure. The tungsten oxide may not be formed on the gate structure so that generation of the whiskers may be suppressed. Thus, a short between adjacent wirings may not be generated.

Abstract: An integrated circuit device, e.g., a memory device, includes a substrate, a first insulation layer on the substrate, and a contact pad disposed in the first insulation layer in direct contact with the substrate. A second insulation layer is disposed on the first insulation layer. A conductive pattern, e.g., a damascene bit line, is disposed in the second insulation layer. A conductive plug extends through the second insulation layer to contact the contact pad and is self-aligned to the conductive pattern. An insulation film may separate the conductive pattern and the conductive plug. A glue layer may be disposed between the conductive pattern and the second insulation layer. The device may further include a third insulation layer on the second insulation layer and the conductive pattern, and the conductive plug may extend through the second and third insulation layers.

Abstract: Methods of forming a semiconductor device may include forming a tunnel oxide layer on a semiconductor substrate, forming a gate structure on the tunnel oxide layer, forming a leakage barrier oxide, and forming an insulating spacer. More particularly, the tunnel oxide layer may be between the gate structure and the substrate, and the gate structure may include a first gate electrode on the tunnel oxide layer, an inter-gate dielectric on the first gate electrode, and a second gate electrode on the inter-gate dielectric with the inter-gate dielectric between the first and second gate electrodes. The leakage barrier oxide may be formed on sidewalls of the second gate electrode. The insulating spacer may be formed on the leakage barrier oxide with the leakage barrier oxide between the insulating spacer and the sidewalls of the second gate electrode. In addition, the insulating spacer and the leakage barrier oxide may include different materials. Related structures are also discussed.

Abstract: A gate structure includes a gate insulation layer on a substrate, a polysilicon layer pattern on the gate insulation layer, a composite metal layer pattern on the polysilicon layer pattern, and a metal silicide layer pattern on a sidewall of the composite metal layer pattern.

Abstract: Methods of forming semiconductor devices are provided. A preliminary gate structure is formed on a semiconductor substrate. The preliminary gate structure includes a gate insulation layer pattern, a polysilicon layer pattern and a conductive layer pattern. A first oxidation process is performed on the preliminary gate structure using an oxygen radical. The first oxidation process is carried out at a first temperature. A second oxidation process is carried out on the oxidized preliminary gate structure to provide a gate structure on the substrate, the second oxidation process being carried out at a second temperature, the second temperature being higher than the first temperature.

Abstract: A semiconductor device includes a first conductive layer on a semiconductor substrate, a dielectric layer including a high-k dielectric material on the first conductive layer, a second conductive layer including polysilicon doped with P-type impurities on the dielectric layer, and a third conductive layer including a metal on the second conductive layer. In some devices, a first gate structure is formed in a main cell region and includes a tunnel oxide layer, a floating gate, a first high-k dielectric layer, and a control gate. The control gate includes a layer of polysilicon doped with P-type impurities and a metal layer. A second gate structure is formed outside the main cell region and includes a tunnel oxide layer, a conductive layer, and a metal layer. A third gate structure is formed in a peripheral cell region and includes a tunnel oxide, a conductive layer, and a high-k dielectric layer having a width narrower than the conductive layer. Method embodiments are also disclosed.

Abstract: In methods of manufacturing semiconductor devices, a preliminary gate oxide layer is formed on a substrate. A surface treatment process is performed on the preliminary gate oxide layer that reduces a diffusion of an oxidizing agent in the preliminary gate oxide layer to form a gate oxide layer on the substrate. A preliminary gate structure is formed on the gate oxide layer. The preliminary gate structure includes a first conductive layer pattern on the gate oxide layer and a second conductive layer pattern on the first conductive layer pattern. An oxidation process is performed on the preliminary gate structure using the oxidizing agent to form an oxide layer on a sidewall of the first conductive layer pattern and on the gate oxide layer, and to round at least one edge portion of the first conductive layer pattern.