Abstract: The present invention relates to a multi-functional support pole assembly. In particular, the present invention provides the advantage of improving operational reliability as well as preventing deterioration of urban area appearance, by comprising: a pole body provided in a hollow form and having a plurality of antenna mounting grooves formed through cutting so as to be spaced apart at a predetermined angle in a circumferential direction such that a plurality of antenna devices can be installed in the circumferential direction; and ventilation panels which are attached to remaining portions of the antenna mounting grooves not occupied by the plurality of antenna devices, and have a plurality of ventilation holes for introducing external air into the interior of the pole body.

Abstract: A wireless communication device support assembly is disclosed, including a support pole comprising a hollow interior, a first frame having a polygonal shape disposed on top of the support pole, a plurality of wireless communication devices disposed inside the first frame, at least one or more rotational advertising apparatuses controllably elevated in a direction parallel to a longitudinal direction of the support pole, a drive unit configured to elevate or lower the rotational advertising apparatus, and a plurality of lift ropes having first ends connected with tops of the rotational advertising apparatuses and second ends connected with the drive unit.

Abstract: The present invention relates to a support pole assembly for mounting an antenna and, particularly, to a support pole assembly for mounting an antenna, comprising: a support pole which is formed in a hollow structure and has an antenna device mounting hole formed at the circumferential surface thereof; an antenna device which is mounted to the support pole while passing through and covering the antenna device mounting hole and the rear portion of which is placed in the inner space of the support pole. Accordingly, the present invention provides an advantage in that the protrusion amount of the antenna device with respect to the support pole is reduced and thus the space required for mounting the antenna device can be reduced.

Abstract: Disclosed are a display panel and a display device including the same according to an embodiment. A display panel according to the embodiment includes: a display area in which a plurality of first pixels are arranged at a first pixels per inch (PPI); and a sensing area in which a plurality of second pixels are arranged at a second PPI that is lower than the first PPI, wherein the first pixels of the display area and the second pixels of the sensing area are arranged adjacent to each other at a boundary between the display area and the sensing area, the second pixel includes red, green, and blue sub-pixels, and at least one of the red and green sub-pixels of the second pixel is arranged closest to the first pixel.

Abstract: The present disclosure relates to a hot-rolled steel sheet utilized as material for heavy machinery, vehicle frames, and the like, and more specifically to a high-strength hot-rolled steel sheet having excellent bendability and low-temperature toughness and a method for manufacturing same.

Abstract: The present disclosure relates to a hot-rolled steel sheet utilized as material for heavy machinery, vehicle frames, and the like, and more specifically to a high-strength hot-rolled steel sheet having excellent bendability and low-temperature toughness and a method for manufacturing same.

Abstract: The present disclosure relates to a hot-rolled steel sheet utilized as material for heavy machinery, vehicle frames, and the like, and more specifically to a high-strength hot-rolled steel sheet having excellent bendability and low-temperature toughness and a method for manufacturing same.

Abstract: An electronic device is provided to comprise a semiconductor memory unit that comprises: a substrate including active regions, which are extended in a second direction and disposed from each other in a first direction; a plurality of gates extended in the first direction and across with the active regions; a lower contact disposed in both sides of gates and coupling the active regions in the first direction; an upper contact of the lower contact overlapping with the active region out of the active regions in a side of each gate, and overlapping with the active regions in the other side of each gate; and first and second interconnection lines coupled to the upper contact, extended in the second direction, and being alternately disposed from each other in the first direction, wherein the upper contact of a side of the gates has a zigzag shape in a first oblique direction.

Abstract: An electronic device is provided to comprise a semiconductor memory unit that comprises: a substrate including active regions, which are extended in a second direction and disposed from each other in a first direction; a plurality of gates extended in the first direction and across with the active regions; a lower contact disposed in both sides of gates and coupling the active regions in the first direction; an upper contact of the lower contact overlapping with the active region out of the active regions in a side of each gate, and overlapping with the active regions in the other side of each gate; and first and second interconnection lines coupled to the upper contact, extended in the second direction, and being alternately disposed from each other in the first direction, wherein the upper contact of a side of the gates has a zigzag shape in a first oblique direction.

Abstract: An electronic device is provided to comprise a semiconductor memory unit that comprises: a substrate including active regions, which are extended in a second direction and disposed from each other in a first direction; a plurality of gates extended in the first direction and across with the active regions; a lower contact disposed in both sides of gates and coupling the active regions in the first direction; an upper contact of the lower contact overlapping with the active region out of the active regions in a side of each gate, and overlapping with the active regions in the other side of each gate; and first and second interconnection lines coupled to the upper contact, extended in the second direction, and being alternately disposed from each other in the first direction, wherein the upper contact of a side of the gates has a zigzag shape in a first oblique direction.

Abstract: A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.

Abstract: An electronic device is provided to comprise a semiconductor memory unit that comprises: a substrate including active regions, which are extended in a second direction and disposed from each other in a first direction; a plurality of gates extended in the first direction and across with the active regions; a lower contact disposed in both sides of gates and coupling the active regions in the first direction; an upper contact of the lower contact overlapping with the active region out of the active regions in a side of each gate, and overlapping with the active regions in the other side of each gate; and first and second interconnection lines coupled to the upper contact, extended in the second direction, and being alternately disposed from each other in the first direction, wherein the upper contact of a side of the gates has a zigzag shape in a first oblique direction.

Abstract: A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.

Abstract: A semiconductor device includes a first conductive layer; a second conductive layer; and a resistance variable element interposed between the first conductive layer and the second conductive layer and includes a doped first metal oxide layer and a second metal oxide layer. A density of oxygen vacancies of the second metal oxide layer is higher than that of the doped first metal oxide layer. The doped first metal oxide layer includes a doping material implanted thereto to suppress grains in the doped first metal oxide layer from increasing in size.

Abstract: The present disclosure relates to nitride semiconductor and a fabricating method thereof, and a nitride semiconductor according to an exemplary embodiment of the present disclosure includes a nitride based first and second electrode placed with a distance on a substrate, a nitride based channel layer which connects the first and second electrode, an insulating layer which covers the channel layer, and a third electrode which is formed to cover the insulating layer on the insulating layer.

Abstract: A semiconductor device includes a logic region disposed in a central region of the semiconductor device, and a peripheral region disposed in an outer region thereof. The logic region includes a line-shaped logic transistor and a box-shaped decoupling capacitor. The peripheral region includes a line-shaped peripheral transistor and a line-shaped peripheral dummy transistor disposed adjacent to the peripheral transistor.

Abstract: A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.

Abstract: A semiconductor device includes a first conductive layer; a second conductive layer; and a resistance variable element interposed between the first conductive layer and the second conductive layer and includes a doped first metal oxide layer and a second metal oxide layer. A density of oxygen vacancies of the second metal oxide layer is higher than that of the doped first metal oxide layer. The doped first metal oxide layer includes a doping material implanted thereto to suppress grains in the doped first metal oxide layer from increasing in size.

Abstract: A method of forming a pattern in a semiconductor device is described. A substrate divided into cell and peripheral regions is provided, and an object layer is formed on a substrate. A buffer pattern is formed on the object layer in the cell region along a first direction. A spacer is formed along a sidewall of the buffer pattern in the cell region, and a hard mask layer remains on the object layer in the peripheral region. The buffer layer is removed, and the spacer is separated along a second direction different from the first direction, thereby forming a cell hard mask pattern. A peripheral hard mask pattern is formed in the peripheral region. A minute pattern is formed using the cell and peripheral hard mask patterns in the substrate. Therefore, a line width variation or an edge line roughness due to the photolithography process is minimized.

Abstract: The present disclosure relates to nitride semiconductor and a fabricating method thereof, and a nitride semiconductor according to an exemplary embodiment of the present disclosure includes a nitride based first and second electrode placed with a distance on a substrate, a nitride based channel layer which connects the first and second electrode, an insulating layer which covers the channel layer, and a third electrode which is formed to cover the insulating layer on the insulating layer.