Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

Abstract: A semiconductor device including: a metal-insulator-semiconductor (MIS) structure that includes a nitride semiconductor layer, a gate insulator film, and a gate electrode stacked in stated order; and a source electrode and a drain electrode that are disposed to sandwich the gate electrode in a plan view and contact the nitride semiconductor layer. The gate insulator film includes a threshold value control layer that includes an oxynitride film.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

Abstract: A semiconductor device has an MIS structure that includes a semiconductor layer, a gate insulating film on the semiconductor layer, and a gate electrode on the gate insulating film. The gate insulating film has a layered structure that includes a base SiO2 layer and a high-k layer on the base SiO2 layer and containing Hf. The gate electrode has a portion made of a metal material having a work function of higher than 4.6 eV, the portion being in contact with at least the high-k layer.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

Abstract: This X-ray phase contrast imaging apparatus (100) includes an X-ray source (1) that radiates continuous X-rays, a first grating (3) that forms a self-image, a second grating (4), a detector (5) that detects the continuous X-rays, and a third grating (2) arranged between the detector (5) and the first grating 3. The first grating (3), the second grating (4), and the third grating (2) are arranged so as to satisfy conditions of predetermined formulas.

Abstract: A method for manufacturing a semiconductor device includes: thermally-oxidizing a surface of a to-be-processed base made by SiC as body material to form a silicon dioxide film, by supplying gas containing oxidation agent to the surface of the to-be-processed base; exchanging ambient gas containing the oxidation agent after forming the silicon dioxide film, by decreasing a partial pressure of the oxidation agent in the ambient gas to 10 Pa or less; and after exchanging the ambient gas, lowering a temperature of the to-be-processed base.

Abstract: An X-ray phase contrast imaging device of the present invention can change an arrangement pitch of slits related to a multi-slit and an arrangement pitch of phase shift sections related to a phase grating. A positional relationship among the multi-slit 3b, the phase grating, and an FPD is determined based on the arrangement pitch of the slits related to the multi-slit, the arrangement pitch of the phase shift sections related to the phase grating, and an arrangement pitch of detection elements related to the FPD. Among these arrangement pitches, by changing the arrangement pitch of the slits and the arrangement pitch of the phase shift sections, the present invention can change the positional relationship among the multi-slit, the phase grating, and the FPD.

Abstract: [PROBLEM TO BE SOLVED] To provide a radiation phase contrast imaging device having a small device configuration [SOLVING MEANS] The present invention focused on the findings that the distance between the phase grating 5 and the FPD 4 does not need to be the Talbot distance. The distance between the phase grating 5 and the FPD 4 can be more freely set. However, a self-image cannot be detected unless the self-image is sufficiently magnified with respect to the phase grating 5. The degree on how much the self-image is magnified on the FPD 4 with respect to the original phase grating 5 is determined by a magnification ratio X2/X1. Therefore, in the present invention, the magnification ratio is set to be the same as the magnification ratio in a conventional configuration. With this, even if the distance X2 between the radiation source 3 and the FPD 4 is reduced, a situation in which the self-image cannot be detected by the FPD 4 due to the excessively small size thereof does not occur.

Abstract: This X-ray phase contrast imaging apparatus (100) includes an X-ray source (1), a first grating (3) that forms a self-image, a second grating (4), a detector (5) that detects X-rays, an adjustment mechanism (6), and a controller (7) that controls the adjustment mechanism (6) to adjust a misalignment of the first grating (3) or a misalignment of the second grating (4) based on Moire fringes detected by the detector (5).

Abstract: A semiconductor device including: a metal-insulator-semiconductor (MIS) structure that includes a nitride semiconductor layer, a gate insulator film, and a gate electrode stacked in stated order; and a source electrode and a drain electrode that are disposed to sandwich the gate electrode in a plan view and contact the nitride semiconductor layer. The gate insulator film includes a threshold value control layer that includes an oxynitride film.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type. A well region that is a second conductivity type well region is formed on a surface layer portion of the semiconductor layer and has a channel region defined therein. A source region that is a first conductivity type source region is formed on a surface layer portion of the well region. A gate insulating film is formed on the semiconductor layer and has a multilayer structure. A gate electrode is opposed to the channel region of the well region where a channel is formed through the gate insulating film.