Patents by Inventor Heiji Watanabe
Heiji Watanabe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20150318372Abstract: A semiconductor device according to the present invention has a MIS structure that includes a semiconductor layer, a gate insulating film in contact with the semiconductor layer, and a gate electrode formed on the gate insulating film, and the gate insulating film includes an AlON layer with a nitrogen composition of 5% to 40%. A semiconductor device is thereby provided with which electron trapping in the gate insulating film can be reduced and shifting of a threshold voltage Vth can be suppressed.Type: ApplicationFiled: December 2, 2013Publication date: November 5, 2015Inventors: Heiji WATANABE, Takuji HOSOI, Takayoshi SHIMURA, Ryota NAKAMURA, Yuki NAKANO, Shuhei MITANI, Takashi NAKAMURA, Hirokazu ASAHARA
-
Publication number: 20150144967Abstract: A semiconductor device includes a semiconductor layer made of first conductivity type SiC; a second conductivity type well region formed on the semiconductor layer and having a channel region; a first conductivity type source region formed on the well region and including a first region adjacent to the well region and a second region adjacent to the first region; a gate insulating film formed on the semiconductor layer and having a first portion that contacts the first region; a second portion that contacts the well region and that has a thickness that is the same as that of the first portion; and a third portion that contacts the second region and that has a thickness that is greater than that of the first portion; and a gate electrode formed on the gate insulating film and opposed to the channel region where a channel is formed through the gate insulating film.Type: ApplicationFiled: January 21, 2015Publication date: May 28, 2015Inventors: Shuhei MITANI, Yuki NAKANO, Heiji WATANABE, Takayoshi SHIMURA, Takuji HOSOI, Takashi KIRINO
-
Patent number: 8969877Abstract: A semiconductor device includes a semiconductor layer made of first conductivity type SiC; a second conductivity type well region formed on the semiconductor layer and having a channel region; a first conductivity type source region formed on the well region and including a first region adjacent to the well region and a second region adjacent to the first region; a gate insulating film formed on the semiconductor layer and having a first portion that contacts the first region; a second portion that contacts the well region and that has a thickness that is the same as that of the first portion; and a third portion that contacts the second region and that has a thickness that is greater than that of the first portion; and a gate electrode formed on the gate insulating film and opposed to the channel region where a channel is formed through the gate insulating film.Type: GrantFiled: January 7, 2014Date of Patent: March 3, 2015Assignee: Rohm Co., Ltd.Inventors: Shuhei Mitani, Yuki Nakano, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi, Takashi Kirino
-
Publication number: 20150034971Abstract: [Problem] To provide an SiC semiconductor device, with which stabilization of high-temperature operation can be achieved by decreasing mobile ions in a gate insulating film, and a method for manufacturing the SiC semiconductor device. [ Solution Means] A semiconductor device 1 has an MIS structure including an SiC epitaxial layer 3, a gate insulating film 9 and a gate electrode 10 formed on the gate insulating film 9. A gate insulating film 9 includes a silicon oxide film in contact with the SiC epitaxial layer 3. In the MIS structure, an area density QM of positive mobile ions in the gate insulating film 9 is made no more than 1×1012 cm?2.Type: ApplicationFiled: February 22, 2013Publication date: February 5, 2015Inventors: Heiji Watanabe, Takayoshi Sshimura, Takuji Hosoi, Shuhei Mitani, Yuki Nakano, Ryota Nakamura, Takashi Nakamura
-
Publication number: 20140138708Abstract: A method of manufacturing a semiconductor device includes the steps of forming a silicon oxide film on a silicon carbide substrate, annealing the silicon carbide substrate and the silicon oxide film in gas containing hydrogen, and forming an aluminum oxynitride film on the silicon oxide film after the annealing of the silicon carbide substrate and the silicon oxide film.Type: ApplicationFiled: January 7, 2014Publication date: May 22, 2014Applicant: ROHM CO., LTD.Inventors: Shuhei MITANI, Yuki NAKANO, Heiji WATANABE, Takayoshi SHIMURA, Takuji HOSOI, Takashi KIRINO
-
Publication number: 20140094027Abstract: Provided is a method of forming a gate insulating film for use in a MOSFET for a power device. An AlN film is formed on a SiC substrate of a wafer W and then the formation of an AlO film and the formation of an AlN film on the formed AlO film are repeated, thereby forming an AlON film having a laminated structure in which AlO films and AlN films are alternately laminated. A heat treatment is performed on the AlON film having the laminated structure.Type: ApplicationFiled: October 2, 2013Publication date: April 3, 2014Applicants: OSAKA UNIVERSITY, TOKYO ELECTRON LIMITEDInventors: Shuji AZUMO, Yusaku KASHIWAGI, Yuichiro MOROZUMI, Yu WAMURA, Katsushige HARADA, Kosuke TAKAHASHI, Heiji WATANABE, Takayoshi SHIMURA, Takuji HOSOI
-
Patent number: 8669624Abstract: Provided are a semiconductor device which enables reduction of diffusion of Si in the manufacturing process of an MIPS element and suppression of an increase in EOT, and a method of manufacturing the same. An embodiment of the present invention is a semiconductor device including a field effect transistor having a gate insulating film provided on a silicon substrate and a gate electrode provided on the gate insulating film. The gate electrode is a stack-type electrode including a conductive layer containing at least Ti, N, and O (oxygen) and a silicon layer provided on the conductive layer, and the concentration of oxygen in the conductive layer is highest in the side of the silicon layer.Type: GrantFiled: July 26, 2012Date of Patent: March 11, 2014Assignee: Canon Anelva CorporationInventors: Naomu Kitano, Takashi Minami, Nobuo Yamaguchi, Takuya Seino, Takashi Nakagawa, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi
-
Patent number: 8653533Abstract: A method of manufacturing a semiconductor device includes the steps of forming a silicon oxide film on a silicon carbide substrate, annealing the silicon carbide substrate and the silicon oxide film in gas containing hydrogen, and forming an aluminum oxynitride film on the silicon oxide film after the annealing of the silicon carbide substrate and the silicon oxide film.Type: GrantFiled: September 2, 2010Date of Patent: February 18, 2014Assignee: Rohm Co., Ltd.Inventors: Shuhei Mitani, Yuki Nakano, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi, Takashi Kirino
-
Patent number: 8575677Abstract: A semiconductor device having, on a silicon substrate, a gate insulating film and a gate electrode in this order; wherein the gate insulating film comprises a nitrogen containing high-dielectric-constant insulating film which has a structure in which nitrogen is introduced into metal oxide or metal silicate; and the nitrogen concentration in the nitrogen containing high-dielectric-constant insulating film has a distribution in the direction of the film thickness; and a position at which the nitrogen concentration in the nitrogen containing high-dielectric-constant insulating film reaches the maximum in the direction of the film thickness is present in a region at a distance from the silicon substrate. A method of manufacturing a semiconductor device including introducing nitrogen by irradiating the high-dielectric-constant insulating film which is made of metal oxide or metal silicate, with a nitrogen containing plasma, is also provided.Type: GrantFiled: January 18, 2012Date of Patent: November 5, 2013Assignee: Renesas Electronics CorporationInventors: Heiji Watanabe, Kazuhiko Endo, Kenzo Manabe
-
Publication number: 20130285158Abstract: Provided are a semiconductor device which enables reduction of diffusion of Si in the manufacturing process of an MIPS element and suppression of an increase in EOT, and a method of manufacturing the same. An embodiment of the present invention is a semiconductor device including a field effect transistor having a gate insulating film provided on a silicon substrate and a gate electrode provided on the gate insulating film. The gate electrode is a stack-type electrode including a conductive layer containing at least Ti, N, and O (oxygen) and a silicon layer provided on the conductive layer, and the concentration of oxygen in the conductive layer is highest in the side of the silicon layer.Type: ApplicationFiled: July 26, 2012Publication date: October 31, 2013Applicant: CANON ANELVA CORPORATIONInventors: Naomu Kitano, Takashi Minami, Nobuo Yamaguchi, Takuya Seino, Takashi Nakagawa, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi
-
Publication number: 20120223338Abstract: A method of manufacturing a semiconductor device includes the steps of forming a silicon oxide film on a silicon carbide substrate, annealing the silicon carbide substrate and the silicon oxide film in gas containing hydrogen, and forming an aluminum oxynitride film on the silicon oxide film after the annealing of the silicon carbide substrate and the silicon oxide film.Type: ApplicationFiled: September 2, 2010Publication date: September 6, 2012Applicant: Rohm Co. Ltd.Inventors: Shuhei Mitani, Yuki Nakano, Heiji Watanabe, Takayoshi Shimura, Takuji Hosoi, Takashi Kirino
-
Publication number: 20120181632Abstract: A semiconductor device having, on a silicon substrate, a gate insulating film and a gate electrode in this order; wherein the gate insulating film comprises a nitrogen containing high-dielectric-constant insulating film which has a structure in which nitrogen is introduced into metal oxide or metal silicate; and the nitrogen concentration in the nitrogen containing high-dielectric-constant insulating film has a distribution in the direction of the film thickness; and a position at which the nitrogen concentration in the nitrogen containing high-dielectric-constant insulating film reaches the maximum in the direction of the film thickness is present in a region at a distance from the silicon substrate. A method of manufacturing a semiconductor device including introducing nitrogen by irradiating the high-dielectric-constant insulating film which is made of metal oxide or metal silicate, with a nitrogen containing plasma, is also provided.Type: ApplicationFiled: January 18, 2012Publication date: July 19, 2012Applicant: NEC CORPORATIONInventors: Heiji WATANABE, Kazuhiko Endo, Kenzo Manabe
-
Patent number: 8125016Abstract: There is provided a semiconductor device having, on a silicon substrate, a gate insulating film and a gate electrode in this order; wherein the gate insulating film comprises a nitrogen containing high-dielectric-constant insulating film which has a structure in which nitrogen is introduced into metal oxide or metal silicate; and the nitrogen concentration in the nitrogen containing high-dielectric-constant insulating film has a distribution in the direction of the film thickness; and a position at which the nitrogen concentration in the nitrogen containing high-dielectric-constant insulating film reaches the maximum in the direction of the film thickness is present in a region at a distance from the silicon substrate. A manufacturing method of a semiconductor device comprising the step of making the introduction of nitrogen by irradiating the high-dielectric-constant insulating film which is made of metal oxide or metal silicate, with a nitrogen containing plasma, is also provided.Type: GrantFiled: June 19, 2003Date of Patent: February 28, 2012Assignee: Renesas Electronics CorporationInventors: Heiji Watanabe, Kazuhiko Endo, Kenzo Manabe
-
Patent number: 8088678Abstract: A first aspect of the present invention provides a semiconductor manufacturing apparatus including: a load lock chamber; a transfer chamber; and a treatment chamber 1 and a treatment chamber 2 which carry out treatment using plasma, wherein, in the treatment chamber 2, an exhaust means is provided with a control means for making an oxygen partial pressure into 1*10?5 [Pa] or less.Type: GrantFiled: December 4, 2009Date of Patent: January 3, 2012Assignee: Canon Anelva CorporationInventors: Naomu Kitano, Takashi Minami, Motomu Kosuda, Heiji Watanabe
-
Patent number: 8026143Abstract: The object of the present invention is to provide a method of manufacturing high permittivity gate dielectrics for a device such as an MOSFET. A HfSiO film is formed by sputtering a Hf metal film on a SiO2 film (or a SiON film) on a Si wafer. A TiO2 film is formed by sputtering a Ti metal film on the HfSiO film and subjecting the Ti metal film to a thermal oxidation treatment. A TiN metal film is deposited on the TiO2 film. The series of treatments are performed continuously, without exposing the films and the wafer to atmospheric air. The resultant TiN/TiO2/HfSiO/SiO2/Si structure satisfies the conditions: EOT<1.0 nm, low leakage current, and hysteresis <20 mV.Type: GrantFiled: November 1, 2007Date of Patent: September 27, 2011Assignee: Canon Anelva CorporationInventors: Naomu Kitano, Takashi Minami, Motomu Kosuda, Heiji Watanabe
-
Publication number: 20100120238Abstract: A first aspect of the present invention provides a semiconductor manufacturing apparatus including: a load lock chamber; a transfer chamber; and a treatment chamber 1 and a treatment chamber 2 which carry out treatment using plasma, wherein, in the treatment chamber 2, an exhaust means is provided with a control means for making an oxygen partial pressure into 1*10?5 [Pa] or less.Type: ApplicationFiled: December 4, 2009Publication date: May 13, 2010Applicant: CANON ANELVA CORPORATIONInventors: Naomu Kitano, Takashi Minami, Motomu Kosuda, Heiji Watanabe
-
Patent number: 7679148Abstract: The task of the present invention is to enable formation of a gate insulating film structure having a good-quality interface between a silicon oxide film and silicon in an interface between a high dielectric constant thin film and a silicon substrate to provide a semiconductor device and a semiconductor manufacturing method which are capable of improving interface electrical characteristics, which has been a longstanding task in practical use of a high dielectric constant insulating film. A metal layer deposition process and a heat treatment process which supply metal elements constituting a high dielectric constant film on a surface of a base silicon oxide film 103 allow the metal elements to be diffused into the base silicon oxide film 103 to thereby form an insulating film structure 105 as a gate insulating film, after forming the base silicon oxide film 103 on a surface of a silicon substrate 101.Type: GrantFiled: July 16, 2003Date of Patent: March 16, 2010Assignee: NEC CorporationInventors: Heiji Watanabe, Hirohito Watanabe, Toru Tatsumi, Shinji Fujieda
-
Publication number: 20090170300Abstract: The object of the present invention is to provide a method of manufacturing high permittivity gate dielectrics for a device such as an MOSFET. A HfSiO film 104 is formed by sputtering a Hf metal film 103 on a SiO2 film (or a SiON film) 102 on a Si wafer 101. A TiO2 film 106 is formed by sputtering a Ti metal film 105 on the HfSiO film 104 and subjecting the Ti metal film 105 to a thermal oxidation treatment. A TiN metal film 107 is deposited on the TiO2 film 106. The series of treatments are performed continuously, without exposing the films and the wafer to atmospheric air. The resultant TiN/TiO2/HfSiO/SiO2/Si structure satisfies the conditions: EOT<1.0 nm, low leakage current, and hysteresis<20 mV.Type: ApplicationFiled: February 27, 2009Publication date: July 2, 2009Applicant: CANON ANELVA CORPORATIONInventors: Naomu Kitano, Takashi Minami, Motomu Kosuda, Heiji Watanabe
-
Patent number: 7495264Abstract: A semiconductor device has a substrate and a dielectric film formed directly or indirectly on the substrate. The dielectric film contains a metal silicate film, and a silicon concentration in the metal silicate film is lower in a center portion in the film thickness direction than in an upper portion and in a lower portion.Type: GrantFiled: December 7, 2006Date of Patent: February 24, 2009Assignee: NEC CorporationInventors: Heiji Watanabe, Haruhiko Ono, Nobuyuki Ikarashi
-
Publication number: 20080305597Abstract: The object of the present invention is to provide a method of manufacturing high permittivity gate dielectrics for a device such as an MOSFET. A HfSiO film 104 is formed by sputtering a Hf metal film 103 on a SiO2 film (or a SiON film) 102 on a Si wafer 101. A TiO2 film 106 is formed by sputtering a Ti metal film 105 on the HfSiO film 104 and subjecting the Ti metal film 105 to a thermal oxidation treatment. A TiN metal film 107 is deposited on the TiO2 film 106. The series of treatments are performed continuously, without exposing the films and the wafer to atmospheric air. The resultant TiN/TiO2/HfSiO/SiO2/Si structure satisfies the conditions: EOT<1.0 nm, low leakage current, and hysteresis<20 mV.Type: ApplicationFiled: November 1, 2007Publication date: December 11, 2008Applicant: CANON ANELVA CORPORATIONInventors: Naomu Kitano, Takashi Minami, Motomu Kosuda, Heiji Watanabe