Patents by Inventor Heimo Hofer

Heimo Hofer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200203525
    Abstract: A transistor device with a gate electrode in a vertical gate trench is described. The gate electrode includes a silicon gate region and a metal inlay region. The silicon gate region forms at least a section of a sidewall of the gate electrode. The metal inlay region extends up from a lower end of the gate electrode.
    Type: Application
    Filed: December 17, 2019
    Publication date: June 25, 2020
    Inventors: Robert Paul Haase, Jyotshna Bhandari, Heimo Hofer, Ling Ma, Ashita Mirchandani, Harsh Naik, Martin Poelzl, Martin Henning Vielemeyer, Britta Wutte
  • Publication number: 20200111896
    Abstract: A method of forming recess for a trench gate electrode includes forming a trench in a first major surface of a semiconductor substrate, the trench having a base and a side wall extending from the base to the first major surface, forming a first insulating layer on the base and the side wall of the trench, inserting a first conductive material into the trench that at least partially covers the first insulation layer to form a field plate in a lower portion of the trench, applying a second insulating layer to the first major surface and the trench such that the second insulating layer fills the trench and covers the conductive material, removing the second insulating layer from the first major surface and partially removing the second insulating layer from the trench by etching and forming a recess for a gate electrode in the second insulating layer in the trench.
    Type: Application
    Filed: October 8, 2019
    Publication date: April 9, 2020
    Inventors: Thomas Feil, Jyotshna Bhandari, Christoph Gruber, Heimo Hofer, Ravi Keshav Joshi, Olaf Kuehn, Juergen Steinbrenner
  • Patent number: 10249723
    Abstract: A semiconductor device includes a semiconductor body having a main surface and an active region surrounded by a non-active region. A trench extends from the main surface into the semiconductor body. The trench has a stripe configuration and extends laterally within the active region. A first electrode and a first insulator are in the trench. The first insulator insulates the first electrode from the semiconductor body. The first electrode is recessed in the trench and has a planar surface extending generally parallel with and below the main surface of the semiconductor body so as to define a well in the trench that is laterally confined by the first insulator. A second insulator is on the planar surface. A second electrode is within the well of the trench, and the second insulator insulates the second electrode from the first electrode.
    Type: Grant
    Filed: December 26, 2017
    Date of Patent: April 2, 2019
    Assignee: Infineon Technologies Austria AG
    Inventors: Heimo Hofer, Martin Poelzl, Maximilian Roesch, Britta Wutte
  • Publication number: 20180247820
    Abstract: A method for depositing an insulating layer includes performing a primary deposition over a sidewall of a feature by depositing a layer of silicate glass using a silicon source at a first flow rate and a dopant source at a second flow rate. The method further includes performing a secondary deposition over the sidewall of a feature by increasing the flow of the silicon source relative to the flow of the dopant source. A reflow process is performed after stopping the flow. A variation in thickness of the layer of silicate glass over the sidewall of a feature after the reflow process is between 1% to 20%.
    Type: Application
    Filed: April 27, 2018
    Publication date: August 30, 2018
    Inventors: Juergen Steinbrenner, Markus Kahn, Helmut Schoenherr, Ravi Keshav Joshi, Heimo Hofer, Martin Poelzl, Harald Huetter
  • Publication number: 20180138278
    Abstract: A semiconductor device includes a semiconductor body having a main surface and an active region surrounded by a non-active region. A trench extends from the main surface into the semiconductor body. The trench has a stripe configuration and extends laterally within the active region. A first electrode and a first insulator are in the trench. The first insulator insulates the first electrode from the semiconductor body. The first electrode is recessed in the trench and has a planar surface extending generally parallel with and below the main surface of the semiconductor body so as to define a well in the trench that is laterally confined by the first insulator. A second insulator is on the planar surface. A second electrode is within the well of the trench, and the second insulator insulates the second electrode from the first electrode.
    Type: Application
    Filed: December 26, 2017
    Publication date: May 17, 2018
    Inventors: Heimo Hofer, Martin Poelzl, Maximilian Roesch, Britta Wutte
  • Patent number: 9859385
    Abstract: A method of processing a semiconductor device is presented. The method includes providing a semiconductor body; forming a trench within the semiconductor body, the trench having a stripe configuration and extending laterally within an active region of the semiconductor body that is surrounded by a non-active region of the semiconductor body; forming, within the trench, a first electrode and a first insulator insulating the first electrode from the semiconductor body; carrying out a first etching step for partially removing the first electrode along the total lateral extension of the first electrode such that the remaining part of the first electrode has a planar surface, thereby creating a well in the trench that is laterally confined by the first insulator; depositing a second insulator on top the planar surface; and forming a second electrode within the well of the trench. The second insulator insulates the second electrode from the first electrode.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: January 2, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Heimo Hofer, Martin Poelzl, Maximilian Roesch, Britta Wutte
  • Publication number: 20170236913
    Abstract: A method of processing a semiconductor device includes: creating first and second recesses in a surface of a semiconductor body; creating an insulation layer that forms first and second wells each having a common lateral extension range with the portion of the insulation layer located between the recesses; filling the wells with a plug material having the respective common lateral extension range with the insulation layer; removing a middle portion of the insulation layer located between the recesses; filling, with a filling material, a third recess created in a region where the middle portion has been removed and at least a portion of the space located between the wells; creating a first common surface of the insulation layer, the plug material, and the filling material; removing the plug material from the second well; and creating a second insulation layer that covers a side wall of the second recess.
    Type: Application
    Filed: February 8, 2017
    Publication date: August 17, 2017
    Inventors: Heimo Hofer, Martin Poelzl, Britta Wutte
  • Publication number: 20170207309
    Abstract: A method of processing a semiconductor device is presented. The method includes providing a semiconductor body; forming a trench within the semiconductor body, the trench having a stripe configuration and extending laterally within an active region of the semiconductor body that is surrounded by a non-active region of the semiconductor body; forming, within the trench, a first electrode and a first insulator insulating the first electrode from the semiconductor body; carrying out a first etching step for partially removing the first electrode along the total lateral extension of the first electrode such that the remaining part of the first electrode has a planar surface, thereby creating a well in the trench that is laterally confined by the first insulator; depositing a second insulator on top the planar surface; and forming a second electrode within the well of the trench. The second insulator insulates the second electrode from the first electrode.
    Type: Application
    Filed: January 13, 2017
    Publication date: July 20, 2017
    Inventors: Heimo Hofer, Martin Poelzl, Maximilian Roesch, Britta Wutte
  • Publication number: 20170011927
    Abstract: A method for depositing an insulating layer includes performing a primary deposition over a sidewall of a feature by depositing a layer of silicate glass using a silicon source at a first flow rate and a dopant source at a second flow rate. A ratio of the flow of the dopant source to the flow of the silicon source is a first ratio. The method further includes performing a secondary deposition over the sidewall of a feature by increasing the flow of the silicon source relative to the flow of the dopant source. The ratio of the flow of the dopant source to the flow of the silicon source is a second ratio lower than the first ratio, and stopping the flow of the silicon source after performing the secondary deposition. A reflow process is performed after stopping the flow. A variation in thickness of the layer of silicate glass over the sidewall of a feature after the reflow process is between 1% to 20%.
    Type: Application
    Filed: September 22, 2016
    Publication date: January 12, 2017
    Inventors: Juergen Steinbrenner, Markus Kahn, Helmut Schoenherr, Ravi Joshi, Heimo Hofer, Martin Poelzl, Harald Huetter
  • Patent number: 9455136
    Abstract: A method for depositing an insulating layer includes performing a primary deposition over a sidewall of a feature by depositing a layer of silicate glass using a silicon source at a first flow rate and a dopant source at a second flow rate. A ratio of the flow of the dopant source to the flow of the silicon source is a first ratio. The method further includes performing a secondary deposition over the sidewall of a feature by increasing the flow of the silicon source relative to the flow of the dopant source. The ratio of the flow of the dopant source to the flow of the silicon source is a second ratio lower than the first ratio, and stopping the flow of the silicon source after performing the secondary deposition. A reflow process is performed after stopping the flow. A variation in thickness of the layer of silicate glass over the sidewall of a feature after the reflow process is between 1% to 20%.
    Type: Grant
    Filed: January 23, 2015
    Date of Patent: September 27, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Juergen Steinbrenner, Markus Kahn, Helmut Schoenherr, Ravi Joshi, Heimo Hofer, Martin Poelzl, Harald Huetter
  • Publication number: 20160218002
    Abstract: A method for depositing an insulating layer includes performing a primary deposition over a sidewall of a feature by depositing a layer of silicate glass using a silicon source at a first flow rate and a dopant source at a second flow rate. A ratio of the flow of the dopant source to the flow of the silicon source is a first ratio. The method further includes performing a secondary deposition over the sidewall of a feature by increasing the flow of the silicon source relative to the flow of the dopant source. The ratio of the flow of the dopant source to the flow of the silicon source is a second ratio lower than the first ratio, and stopping the flow of the silicon source after performing the secondary deposition. A reflow process is performed after stopping the flow. A variation in thickness of the layer of silicate glass over the sidewall of a feature after the reflow process is between 1% to 20%.
    Type: Application
    Filed: January 23, 2015
    Publication date: July 28, 2016
    Inventors: Juergen Steinbrenner, Markus Kahn, Helmut Schoenherr, Ravi Joshi, Heimo Hofer, Martin Poelzl, Harald Huetter
  • Patent number: 8728891
    Abstract: Contact openings are produced in a semiconductor body by forming a plurality of self-aligned structures on a main surface of a semiconductor body, each self-aligned structure filling a trench formed in the semiconductor body and extending above and onto the main surface. Adjacent ones of the self-aligned structures have spaced apart sidewalls which face each other. A spacer layer is formed on the sidewalls of the self-aligned structures. Openings are formed in the semiconductor body between adjacent ones of the self-aligned structures while the spacer layer is on the sidewalls of the self-aligned structures. Each opening has a width and a distance to the sidewall of an adjacent trench which corresponds to a thickness of the spacer layer. Self-aligned contact structures can also be produced on a semiconductor body, with or without using the spacer layer.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: May 20, 2014
    Assignee: Infineon Technologies Austria AG
    Inventors: Heimo Hofer, Martin Poelzl
  • Publication number: 20120315759
    Abstract: Contact openings are produced in a semiconductor body by forming a plurality of self-aligned structures on a main surface of a semiconductor body, each self-aligned structure filling a trench formed in the semiconductor body and extending above and onto the main surface. Adjacent ones of the self-aligned structures have spaced apart sidewalls which face each other. A spacer layer is formed on the sidewalls of the self-aligned structures. Openings are formed in the semiconductor body between adjacent ones of the self-aligned structures while the spacer layer is on the sidewalls of the self-aligned structures. Each opening has a width and a distance to the sidewall of an adjacent trench which corresponds to a thickness of the spacer layer. Self-aligned contact structures can also be produced on a semiconductor body, with or without using the spacer layer.
    Type: Application
    Filed: July 27, 2012
    Publication date: December 13, 2012
    Applicant: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Heimo Hofer, Martin Poelzl
  • Patent number: 7005351
    Abstract: A method for fabricating a transistor configuration including at least one trench transistor cell has a gate electrode and a field electrode disposed in a trench below the gate electrode. The trenches are formed in a semiconductor substrate. A drift zone, a channel zone, and a source zone are in each case provided in the semiconductor substrate. According to the invention, the source zone and/or the channel zone are formed at the earliest after the introduction of the trenches into the semiconductor substrate by implantation and diffusion.
    Type: Grant
    Filed: March 19, 2003
    Date of Patent: February 28, 2006
    Assignee: Infineon Technologies AG
    Inventors: Ralf Henninger, Franz Hirler, Joachim Krumrey, Walter Rieger, Martin Pƶlzl, Heimo Hofer
  • Publication number: 20040031987
    Abstract: A method for fabricating a transistor configuration including at least one trench transistor cell has a gate electrode and a field electrode disposed in a trench below the gate electrode. The trenches are formed in a semiconductor substrate. A drift zone, a channel zone, and a source zone are in each case provided in the semiconductor substrate. According to the invention, the source zone and/or the channel zone are formed at the earliest after the introduction of the trenches into the semiconductor substrate by implantation and diffusion.
    Type: Application
    Filed: March 19, 2003
    Publication date: February 19, 2004
    Inventors: Ralf Henninger, Franz Hirler, Joachim Krumrey, Walter Rieger, Martin Polzl, Heimo Hofer