Abstract: Methods and devices are disclosed involving crosstalk reduction depending on weighting factors or grouping of transmission channels. In other embodiments, other methods or devices may be used.

Abstract: In an embodiment, a communication device is provided comprising transmit circuitry and crosstalk reduction circuitry. In an embodiment, the crosstalk reduction circuitry is configured to receive crosstalk information indicative of crosstalk between a plurality of communication connections for only a part of communication channels of said communication connections.

Abstract: Embodiments related to FEXT estimation and signaling in vectored systems are described and depicted herein.

Abstract: Embodiments related to probing and estimation of cross-coupling in a Vector transmission system are described and depicted.

Abstract: Embodiments related to communication of data in a first and second transmission mode are depicted and described herein.

Abstract: In a method of transmission power control, transmission powers of transmission channels and/or transmission power spectral densities are adjusted so as to improve the transmission characteristics.

Abstract: Embodiments related to determining of coupling coefficients in a Vector transmission system are described and depicted.

Abstract: A method includes providing first values depending on crosstalk among a plurality of transmission links. A number of crosstalk channels are selected from a plurality of crosstalk channels interfering with signal transmission on transmissions links. The selecting depends on the first values.

Abstract: A device is provided for measuring properties of transmission links by an adaptive filter. The device comprises a first output terminal adapted to provide a first signal to the transmission link. Further, the device includes a first input terminal for receiving an echo signal of the first signal. An adaptive filter forms a part of the device and is coupled to the first input terminal. The device includes a second output terminal for providing information identifying filter coefficient of the adaptive filter.

Abstract: Fractional Spaced Equalizer FSEQ having adjustable coefficients ci for equalizing a reception signal of a transceiver. The transceiver comprises an echo compensator EC which generates an echo compensation signal for compensating an echo signal of the transceiver. The echo compensation signal is subtracted from the reception signal equalized by the fractional spaced equalizer FSEQ by means of a subtractor and the adjustable coefficients ci of the fractional spaced equalizer FSEQ are set after a half-duplex training phase of the transceiver during which the echo compensator EC is deactivated.

Abstract: Implementations related to transmission systems are presented herein.

Abstract: A splitter circuit (19) serves to combine on the transmission side signals which are to be transmitted in different frequency bands (A-C), as well as to separate on the reception side these signals which are transmitted in different frequency bands. For this purpose, the splitter circuit (19) has a circuit section (13) designed as purely passive, for the rough signal and impedance separation, as well as the filters (3, 4; 9, 10) allocated to the individual transmission and reception sections, for the exact filtering out of the individual signal in each case. These separate filters (3, 4; 9, 10) are arranged in the transmission direction upstream of a corresponding four-wire/two-wire conversion, and in the reception direction downstream of a corresponding two-wire/four-wire conversion, so that the signal stream takes place via these filters in one direction only, and the filters can be designed as purely active filters or digital filters.

Abstract: A device has a plurality of output terminals to provide a plurality of signals to a plurality of transmission links; at least one input terminal to receive information representing a projection of a complex valued error signal onto one direction; and a determination circuit, coupled to the at least one input terminal, to determine crosstalk compensation parameters using the received information.

Abstract: A method and apparatus for reducing the crest factor of a signal uses a plurality of partial correction signals having respective predetermined frequencies. For each of the partial correction signals, the following steps are performed: (a) determining a time position of a maximum absolute amplitude of the signal; (b) calculating an amplitude and a phase depending on said maximum absolute amplitude and said time position for the respective partial correction signal; and (c) subtracting the respective partial correction signal from said signal to obtain a partially corrected signal which is used as the signal in step (a) for the next of the plurality of partial correction signals, and going to step (a) for calculating the next partial correction signal. The last-obtained partially corrected signal is output as the reduced-crest factor signal.

Abstract: A method, wherein the following steps are iteratively repeated: providing each of a plurality of signals at a respective one of a plurality of transmission links; transmitting each of the plurality of signals over the respective one of the plurality of transmission links; and measuring signal-to-noise ratios of the plurality of signals transmitted over the plurality of transmission links, wherein an input power level of each of the plurality of signals is set such that the signal-to-noise ratios of the plurality of signals converge when measured after their transmission over the plurality of transmission links.

Abstract: A circuit arrangement for compensating for disturbances in a signal generated by means of discrete multitone modulation includes a multiplicity of adder circuits that are supplied with an error signal vector that is not used for transmitting data via the transmission channel. The multiplicity of adder circuits adds the error signal vector to at least one signal vector to generate an error-corrected signal vector. The circuit arrangement can also include at least one further multiplicity of adder circuits that are supplied with a further error signal vector, the at least one further multiplicity of adder circuits adding the respective further error signal vector to the at least one signal vector to generate a progressively error-corrected signal vector. The circuit arrangement further includes at least one multiplicity of multiplier circuits that precede the at least one multiplicity of adder circuits and multiply the respective error signal vector by adjustable coefficients.

Abstract: The invention relates to a duplex transmission system, wherein an echo compensation signal (yec(k·t)) is generated which is combined with a receive signal (u(t)) to prevent crosstalk from the own transmitter to the receiver. Before feeding the receive signal to the echo compensation device (6, 7), the receive signal is initially scanned with the double symbol rate, equalized and subsequently scanned once again with the simple symbol rate so that only one compensation value per receive signal has to be generated by the echo compensation device (6, 7).

Abstract: A calculation circuit for calculating a sampling phase error is provided. According to one aspect, a calculation circuit includes a first delay element chain having serially connected delay elements, for delaying a digital estimate of a decision device; a second delay element chain having serially connected delay elements, for delaying an equalized signal; a multiplier array which multiplies the undelayed digital estimate and the delayed estimates of all the delay elements of the first delay element chain by the equalized signal and the delayed output signals of all the delay elements of the second delay element chain to generate product signals; a weighting circuit multiplies the product signals generated by the multiplier array by adjustable weighting factors; and having an adder which adds the product signals weighted by the weighting circuit to the sampling phase error signal.

Abstract: A decision feedback equalizer device includes a linear equalizer stage, which has at least one first digital filter with an adjustable first set of coefficients. The equalizer device also includes a decision feedback equalizer stage, which is connected downstream of the linear equalizer stage. The decision feedback equalizer stage includes a summer, to which an output signal of the linear equalizer stage is fed. The decision feedback equalizer stage also includes a decision unit, to which an output signal of the summer is fed. The decision feedback equalizer stage also includes a decision feedback equalizer, to which an output signal of the decision unit is fed and which has at least one second digital filter with an adaptively adjustable second set of coefficients and which supplies an output signal, which is fed to the summer.

Abstract: A clock phase control circuit is provided for controlling the clock phase of a transceiver, having a sampling circuit for sampling an analog received signal with a sampling clock signal; an echo signal compensation circuit for compensating an echo signal which is produced by means of a transmit signal transmitted by the transceiver, it being possible to set the echo signal compensation circuit in an adaptive fashion as a function of a setting signal; a control circuit for generating a control signal for controlling the clock phase, which control signal specifies the phase deviation between the signal phase of the sampling clock signal and a setpoint signal phase of an ideal sampling clock signal; a loop filter for filtering the control signal; a phase counter for generating the sampling clock signal as a function of the filtered control signal described [sic].