Abstract: For digital demodulation of a quadrature amplitude- or phase-modulated signal (xE(t)), this is sampled with a sampling frequency fs and A/D converted, which has the relationship 1 f s = 4 · f 0 1 + 2 · λ

Abstract: The present invention provides a transmission system having a signal source which has an internal resistance, having a signal transmission line (102), one end of which is connected to the signal source, and having a terminating resistance which is connected to another end of the signal transmission line (102), the internal resistance of the signal source and the terminating resistance being complex and being chosen such that frequency-dependent signal attenuation in the transmission system is reduced in a frequency range which contains the frequencies of signals which are produced by the signal source.

Abstract: The system has a demodulator for duplex data transmission with quadrature amplitude modulation via two conductors with two oppositely transporting channels. The channels include an “upper” channel with a higher frequency band fo±Bo/2 and a “lower” channel with a lower frequency band fu±Bu/2. The two frequency bands do not overlap each other. Each of the channels transmits two digital signals at a respective symbol frequency fT, and the received modulated carrier signal is so sampled at a sampling frequency fAo in the case of the upper channel and fAu in the case of the lower channel, respectively. The frequencies are chosen in such a way that fo/fu is a rational number K and fAo=2fo.

Abstract: The circuit arrangement wherein the circuit arrangement includes at least one further multiplicity of first adder circuits which follow the multiplicity of first adder circuits the at least one further multiplicity of first adder circuits in each case being supplied with a further error signal vector and the at least one further multiplicity of first adder circuits adding the respective further error signal vector to the at least one signal vector in order to generate a progressively error-corrected signal vector. The circuit arrangement further includes at least one further multiplicity of first multiplier circuits which precede the at least one further multiplicity of first adder circuits and multiply the respective further error signal vector by adjustable coefficients.

Abstract: A device and method for regulating a sampling rate in a digital data transfer system includes transmitting a synchronizing word used for receiver-side regulation of the sampling rate at regular time intervals. The received signal is filtered by a rate-regulating criterion filter and is simultaneously detected to recognize the synchronizing word. The initial value of the rate-regulating criterion filter controls an adjusting logic for the sampling rate once the synchronizing word is recognized. A rate is formed for the initial value of the rate-regulating criterion filter and the rate undergoes high pass filtering before it is fed to the adjusting logic. An apparatus for controlling the sampling includes a clock control criterion filter, an adjustment logic device, a switch, an apparatus identifying the synchronization word, a magnitude formation circuit, and a high-pass filter. The formation circuit and the high-pass filter are disposed between the criterion filter and the logic device.

Abstract: The invention relates to a decision feedback equalizing device comprising a linear equalizer stage (F1; F2), which has at least one first linear digital filter (F2) with an adjustable first set of coefficients, and comprising a decision feedback equalizer stage (S; E; ERE) that is connected downstream from the linear equalizer stage (F1; F2). Said decision feedback equalizer stage (S; E; ERE) comprises a summer (S) to which an output signal of the linear equalizer stage (F1; F2) can be supplied. The decision feedback equalizer stage also comprises a discriminator (E) to which an output signal of the summer (S) can be supplied and which comprises at least one second digital filter (F2) with an adaptively adjustable second set of coefficients. The decision feedback equalizer stage is additionally provided with a decision feedback equalizer (ERE) to which an output signal of the discriminator (E) can be supplied and which furnishes an output signal that can be supplied to the summer (S).

Abstract: Calculation circuit for calculating a sampling phase error for a decision feedback clock phase regulation circuit, having a first delay element chain (31), which has a plurality of serially connected delay elements, for delaying a digital estimate âK of a decision device; a second delay element chain (32), which has a plurality of serially connected delay elements, for delaying an equalized signal (zk, ek); a multiplier array (33) which consists of multipliers arranged in matrix form and which multiplies the undelayed digital estimate aK and the delayed estimates of all the delay elements of the first delay element chain (31) by the equalized signal (zk, ek) and the delayed output signals of all the delay elements of the second delay element chain (32) in order to generate product signals; a weighting circuit (39) which multiplies the product signals generated by the multiplier array by adjustable weighting factors (bij); and having an adder (41) which adds the product signals weighted by the weighting

Abstract: The invention relates to a method for the compensation of interference in a signal generated by discrete multitone modulation. The signal generated by discrete multitone modulation has a multiplicity of carrier frequencies, and each carrier frequency has a signal vector. An error signal vector is generated from a reference signal vector, which is a signal vector from the multiplicity of signal vectors. The error signal vector is added to each of the remaining signal vectors of the multiplicity of signal vectors for the purpose of compensating for interference. Each of the signal vectors of the multiplicity of signal vectors, except for the reference signal vector, is assigned a set of adjustable coefficients by which the error signal vector is multiplied prior to the addition.

Abstract: A circuit configuration for a QAM transmitter contains a Cordic for converting the baseband signal to the radio frequency band. The complex output signal from the Cordic is converted to the carrier frequency by interpolation filters. Different signal paths can be selected for a lower and an upper frequency band for the carrier signal. The signal paths each use identical filter parts. Therefore, the circuit need be operated at only half the sampling rate of the output signal as far as a multiplexer on the output side.

Abstract: For controlling the sampling timing of a digital data receiver (2) with the aid of a timing control loop (3-6), it is proposed that the timing control criterion (Trk) for the timing control loop is obtained by combining a first portion (Trk1) with a second portion (Trk2). The first portion (Trk1) of the timing control criterion is obtained by evaluating the input and output signals of the decision element (8) of the digital receiver (2), while the second portion (Trk) is obtained by evaluating at least one coefficient (C−1) of the adaptive equaliser (7) of the digital receiver (2). In this way, favourable jitter characteristics and also a stable control response are achieved.

Abstract: A clock phase control circuit is provided for controlling the clock phase of a transceiver, having a sampling circuit for sampling an analog received signal with a sampling clock signal; an echo signal compensation circuit for compensating an echo signal which is produced by means of a transmit signal transmitted by the transceiver, it being possible to set the echo signal compensation circuit in an adaptive fashion as a function of a setting signal; a control circuit for generating a control signal for controlling the clock phase, which control signal specifies the phase deviation between the signal phase of the sampling clock signal and a setpoint signal phase of an ideal sampling clock signal; a loop filter for filtering the control signal; a phase counter for generating the sampling clock signal as a function of the filtered control signal described [sic].

Abstract: A nonlinear echo compensator for an L-level message signal includes a plurality of groups of coefficient memories, wherein each group is assigned to at least one tupel of N successive symbols of the message signal. A selection circuit is connected to a transmit channel in order to receive an outgoing message signal. The selection circuit uses a value, which is currently received, and N−1 preceding symbols of the message signal to select the group associated with the tupel formed by these symbols. A superposition circuit superposes the coefficients of the group, successively and according to a symbol clock, onto a message signal arriving on a receive channel. The echo compensator is particularly suitable for use in a data transmission system in which the symbol pulse duration of the message signal is limited to N*T, where T is the symbol period of the message signal.

Abstract: Digital precoding filter for a transmission filter (6) for minimizing the chrest [sic] factor of the signal (y) output by the transmission filter (6), having a modulo adder 22) of the source data symbols which are received from a data symbol source (2) at a signal input (15) of the precoding filter (4), and added with fedback filtered transmission data symbols to transmission output data symbols (p) which are output to the downstream transmission filter (6) via a signal output (41) of the precoding filter (4); and a digital feedback filter (36) which filters the transmission output data symbols present at the signal output (41) and feeds them back to the modulo adder (22), and that [sic] a digital correction filter (39) is connected to the signal output (41), the filter coefficients of the digital correction filter (39) being set as a function of the normalized pulse response of the transmission filter (6) in the case of that sampling phase (&tgr;) for which the output signal of the transm

Abstract: A method for reducing the crest factor of a signal, the signal being represented by a digital signal vector whose elements are sampled values of the signal. The method includes the steps of calculating a digital correction vector from the elements of the digital signal vector. Adding the digital correction vector and to the digital signal vector, and outputting a corrected digital signal vector.

Abstract: Method and a device for compensating signal echoes during duplex data transmission with discrete multitone modulation

Abstract: A device for changing a noise characteristic in a receiver of a data transmission system that contains a noise predictor that is connected to a noise attenuator. In this configuration, the dimensioning of the noise attenuator is fixed whereas coefficients of the noise predictor can be adaptively adjusted to the respective interference.

Abstract: A circuit configuration for a QAM transmitter contains a Cordic for converting the baseband signal to the radio frequency band. The complex output signal from the Cordic is converted to the carrier frequency by interpolation filters. Different signal paths can be selected for a lower and an upper frequency band for the carrier signal. The signal paths each use identical filter parts. Therefore, the circuit need be operated at only half the sampling rate of the output signal as far as a multiplexer on the output side.

Abstract: The invention relates to a data transmission method in which the data to be transmitted are divided into a plurality of subchannels each with a normal component and a quadrature component that is orthogonal to the normal component. The divided data are transmitted in different frequency bands. The frequency bands are arranged with non-equidistant frequency spacings between one another. An error signal is generated at the reception end for each subchannel both for the normal branch and for the quadrature branch and fed to a corresponding reception filter.

Abstract: The QAM/CAP (quadrature amplitude modulation, carrierless amplitude/phase modulation) receiver has an analog-to-digital converter, a digital level regulator, an adaptive reception filter pair, and a downstream decision maker. The coefficients of the filter pair of the QAM/CAP receiver are adaptively adjusted in that the nth filter coefficient of a filter in the ith adjustment step is reduced by a correction value by the filter coefficient of the previous adjustment step i−1. The correction value is the product of a distortion elimination error, a delayed input value, and a manipulated variable &ggr;.

Abstract: An adaptive CAP filter includes a clock-controlled A/D converter for converting an input signal, a digital level-control circuit, an adaptive controlled reception filtering system with two parallel filters and a downstream decision maker for outputting reconstructed signal coordinates. The digital level-control circuit and the adaptive reception filtering system are decoupled by virtue of the fact that either an adjustment of the digital level-control circuit or a coefficient adjustment of the adaptive reception filtering system is active. A method for controlling a cap receiver is also provided.