Abstract: The present application discloses a display panel, a display panel manufacturing method, and a display device. The display panel includes a source region and a drain region. A dielectric layer covering the source region and the drain region is provided with a first via hole and a second via hole separately. The first via hole is connected to the source region or the drain region, the second via hole is located on the top of the first via hole and is in communication with the first via hole, and an aperture of the second via hole is larger than an aperture of the first via hole.

Abstract: The present application provides an array substrate, a preparation method thereof, and a display device. The array substrate includes a base substrate, a first metal layer, a first insulation layer, a second metal layer, a second insulation layer, and a semiconductor layer. The first metal layer includes a data line, and the second metal layer includes a gate, a scanning line, and a common electrode. The gate is electrically connected to the scanning line. The semiconductor layer includes an active layer and a pixel electrode. The active layer includes a channel region, a source, and a drain, to overlap with the gate to form a driving transistor. The source is electrically connected to the data line through a conductive via hole, and the pixel electrode is electrically connected to the drain. The array substrate is able to effectively reduce parasitic capacitance, which facilitates to improve refresh rate and resolution.

Abstract: A method for preparing an array substrate and an array substrate. The method for preparing an array substrate includes: depositing a first metal layer, an insulating layer, an active layer and a doping layer on the substrate; forming a photoresist on doping layer by using a first photomask process, and etching the photoresist to form a gate and a channel; depositing a second metal layer on the substrate; using the second photomask process to form the source-drain metal layer; depositing a passivation layer on the substrate; using the third photomask process to form a pixel electrode layer.

Abstract: Disclosed is a manufacture method of the array substrate, including: sequentially forming a gate, a gate insulating layer, an active layer, an ohmic contact layer and a metal layer on a substrate, forming a photoetching mask on the metal layer, where thickness of the photoetching mask in a half exposure area of the mask plate is from 2000 ? to 6000 ?; etching the metal layer, the ohmic contact layer and the active layer outside a covering area of the photoetching mask; ashing the photoetching mask for a preset time with an ashing reactant, wherein the ashing reactant comprises oxygen, and the preset time is from 70 seconds to 100 seconds; and sequentially etching the metal layer, the ohmic contact layer and the active layer based on the ashed photoetching mask, and forming a channel region of the array substrate. The present disclosure further discloses an array substrate, and a display panel.

Abstract: An array substrate, a method for manufacturing the array substrate, and a display panel are provided in the disclosure. The method for manufacturing the array substrate includes the following. A gate and a signal trace spaced apart from the gate are formed on a substrate. A gate insulation layer is formed on the substrate. An active layer to-be-processed is formed on the gate insulation layer. A first photoresist layer is formed on the active layer to-be-processed. The active layer to-be-processed is etched to form an active layer, where the first photoresist layer is on a side surface of the active layer away from the gate insulation layer. A second photoresist layer is formed on the gate insulation layer. The gate insulation layer is etched to define a through hole, where the through hole faces the signal trace.

Abstract: An array substrate, a method for manufacturing the array substrate, and a display panel are provided in the disclosure. The method for manufacturing the array substrate includes the following. A gate and a signal trace spaced apart from the gate are formed on a substrate. A gate insulation layer is formed on the substrate. An active layer to-be-processed is formed on the gate insulation layer. A first photoresist layer is formed on the active layer to-be-processed. The active layer to-be-processed is etched to form an active layer, where the first photoresist layer is on a side surface of the active layer away from the gate insulation layer. A second photoresist layer is formed on the gate insulation layer. The gate insulation layer is etched to define a through hole, where the through hole faces the signal trace.

Abstract: The present application discloses a display panel and method of manufacturing thereof. The display panel of the present application includes a substrate, an active switch, a color photoresist layer, a first electrode layer, a light emitting diode, a second electrode layer, an encapsulation layer and a driver circuit. The light emitting diode includes a red light emitting layer, a green light emitting layer and a blue light emitting layer which includes a silicon-germanium quantum dot material.

Abstract: The present application discloses a display panel, a display device and a manufacturing method. The display panel includes light-emitting diodes. The light-emitting diodes includes a blue luminescent layer. The blue luminescent layer includes a germanium silicon quantum dot material. A proportion range of a silicon element in the light-emitting diodes is 65%-90%, and a proportion range of a germanium element is 10%-35%.

Abstract: The present application discloses a display panel, a display panel manufacturing method, and a display device. The display panel includes a source region and a drain region. A dielectric layer covering the source region and the drain region is provided with a first via hole and a second via hole separately. The first via hole is connected to the source region or the drain region, the second via hole is located on the top of the first via hole and is in communication with the first via hole, and an aperture of the second via hole is larger than an aperture of the first via hole.

Abstract: The present application discloses a display panel and method of manufacturing thereof. The display panel of the present application includes a substrate, an active switch, a color photoresist layer, a first electrode layer, a light emitting diode, a second electrode layer, an encapsulation layer and a driver circuit. The light emitting diode includes a red light emitting layer, a green light emitting layer and a blue light emitting layer which includes a silicon-germanium quantum dot material.

Abstract: The present application discloses a display panel, a display device and a manufacturing method. The display panel includes light-emitting diodes. The light-emitting diodes includes a blue luminescent layer. The blue luminescent layer includes a germanium silicon quantum dot material. A proportion range of a silicon element in the light-emitting diodes is 65%-90%, and a proportion range of a germanium element is 10%-35%.

Abstract: The present application discloses a display panel and method of manufacturing thereof. The display panel of the present application includes a substrate, an active switch, a color photoresist layer, a first electrode layer, a light emitting diode, a second electrode layer, an encapsulation layer and a driver circuit. The light emitting diode includes a red light emitting layer, a green light emitting layer and a blue light emitting layer which includes a silicon-germanium quantum dot material.

Abstract: Disclosed is a manufacture method of the array substrate, including: sequentially forming a gate, a gate insulating layer, an active layer, an ohmic contact layer and a metal layer on a substrate, forming a photoetching mask on the metal layer, where thickness of the photoetching mask in a half exposure area of the mask plate is from 2000 ? to 6000 ?; etching the metal layer, the ohmic contact layer and the active layer outside a covering area of the photoetching mask; ashing the photoetching mask for a preset time with an ashing reactant, wherein the ashing reactant comprises oxygen, and the preset time is from 70 seconds to 100 seconds; and sequentially etching the metal layer, the ohmic contact layer and the active layer based on the ashed photoetching mask, and forming a channel region of the array substrate. The present disclosure further discloses an array substrate, and a display panel.

Abstract: A structure of an oxide thin film transistor includes: an oxide semiconducting layer, an etching stopper layer on the oxide semiconducting layer, and a source and a drain on the etching stopper layer. Two vias are formed in the etching stopper layer. The oxide semiconducting layer includes two recesses formed therein to extend through a skin layer of the oxide semiconducting layer and respectively corresponding to the two vias. The two recesses are respectively connected with and in communication with the two vias. The source and the drain are respectively filled in the two vias and the two recesses connected with the two vias to directly connect to and physically contact the oxide semiconducting layer.

Abstract: The present application discloses a display panel and method of manufacturing thereof. The display panel of the present application includes a substrate, an active switch, a color photoresist layer, a first electrode layer, a light emitting diode, a second electrode layer, an encapsulation layer and a driver circuit. The light emitting diode includes a red light emitting layer, a green light emitting layer and a blue light emitting layer which includes a silicon-germanium quantum dot material.

Abstract: A structure of an oxide thin film transistor includes: an oxide semiconducting layer, an etching stopper layer on the oxide semiconducting layer, and a source and a drain on the etching stopper layer. Two vias are formed in the etching stopper layer. The oxide semiconducting layer includes two recesses formed therein to extend through a skin layer of the oxide semiconducting layer and respectively corresponding to the two vias. The two recesses are respectively connected with and in communication with the two vias. The source and the drain are respectively filled in the two vias and the two recesses connected with the two vias to directly connect to and physically contact the oxide semiconducting layer.

Abstract: The portion of the active layer of the thin film transistor, facing the gate electrode, defines a channel region, and the portions of the active layer located at two sides of the channel region are transformed to conductors.

Abstract: The present invention provides a manufacture method and a structure of an oxide thin film transistor. The manufacture method of the structure of the oxide thin film transistor comprises providing a carrier; forming an oxide semiconducting layer (4); forming an etching stopper layer (5); forming two vias (51, 53) in the etching stopper layer (5) to expose the oxide semiconducting layer (4); removing a skin layer of the oxide semiconducting layer (4) in the two vias (51, 53) to form two recesses (41, 43) respectively connecting the two vias (51, 53); forming a source (61) and a drain (63) on the etching stopper layer (5), and the source (61) fills one via (51) and the recess (41) connecting therewith, and the drain (63) fills the other via (53) and the recess (43) connecting therewith; performing a post process.

Abstract: A thin-film transistor array substrate for AMOLED and a manufacturing method thereof are disclosed. The thin-film transistor array substrate includes: a substrate; a plurality of thin-film transistor pixel units mounted on the substrate, each of which includes at least one driving thin-film transistor and at least one switching thin-film transistor; a first electrode pattern layer mounted on the substrate; an insulating layer mounted on the substrate and covering gates of the driving thin-film transistor and the switching thin-film transistor and the first electrode pattern layer; and a second electrode pattern layer mounted on the insulating layer and partially overlapped with the first electrode pattern layer to have an overlapping area and a non-overlapping area; the insulating layer has a larger thickness in the overlapping area and has a smaller thickness in the non-overlapping area.

Abstract: The present disclosure proposes a dual-gate thin film transistor and manufacturing method thereof and an array substrate. A manufacturing method includes: forming a first gate electrode, a gate insulating layer, a semiconductor layer, and an etch stop layer on a first substrate sequentially; forming a drain electrode, an independent electrode, and a source electrode on the exposed semiconductor layer; forming an insulating passivation layer on surfaces of the exposed etch stop layer, the drain electrode, the source electrode, and the independent electrode; and forming a second gate electrode on the insulating passivation layer in an area corresponding to the first gate electrode. The present disclosure can resolve the leakage current problem caused by the effective channel length between the source electrode and the drain electrode to improve the electrical properties of the dual-gate thin film transistor and improve its stability. The present disclosure can simplifies processes and reduce cost.