Abstract: The present invention provides a manufacture method of an oxide semiconductor TFT substrate and a structure thereof. The manufacture method of the dual gate oxide semiconductor TFT substrate utilizes the halftone mask to implement one photo process, which cannot only accomplish the patterning to the oxide semiconductor layer but also obtain the oxide conductor layer (52?) with ion doping process, and the oxide conductor layer (52?) is employed as being the pixel electrode of the LCD to replace the ITO pixel electrode in prior art; the method manufactures the source (81), the drain (82) and the top gate (71) at the same time with one photo process; the method implements patterning process to the passivation layer (8) and the top gate isolation layer (32) together with one photo process, to reduce the number of the photo processes to nine for shortening the manufacture procedure, raising the production efficiency and lowering the production cost.

Abstract: The present invention provides a TFT substrate structure, comprising a Switching TFT and a Driving TFT, and the Switching TFT comprises a first active layer, and the Driving TFT comprises a second active layer, and the first active layer and the second active layer are made by the same or different materials and the electrical properties of the Switching TFT and the Driving TFT are different. According to the different functions of the different TFTs, the present invention employs different working structures for the Switching TFT and the Driving TFT to respectively implement deposition and photolithography, and employs different materials for the active layers of the Switching TFT and the Driving TFT to differentiate the electrical properties of different TFTs in the TFT substrate. Accordingly, the accurate control to the OLED with lowest cost can be realized.

Abstract: The present invention provides a manufacture method of a thin film transistor backplane, comprising steps of: providing a substrate (20) with a gate (21), an insulation layer (22) and a semiconducting layer (23); sequentially forming a second metal layer, a reflecting electrode layer and a conductive oxide layer on the substrate (20); implementing one photolithographic process to the second metal layer, the reflecting electrode layer and the conductive oxide layer to pattern the second metal layer, the reflecting electrode layer and the conductive oxide layer for respectively forming a source/a drain (253), a reflecting electrode (252) and a pixel electrode (251), and the source/the drain (253) are connected to the semiconducting layer (23; forming a protective layer on the source/the drain (253), the reflecting electrode (252) and the pixel electrode (251; forming a flat and pixel defining layer (27) on the protective layer (26); forming a photospacer (28) on the flat and pixel defining layer (27).

Abstract: The present invention provides a manufacture method of an oxide semiconductor TFT substrate and a structure thereof.

Abstract: The present invention provides a manufacture method of an oxide semiconductor TFT substrate and a structure thereof. The manufacture method of the dual gate oxide semiconductor TFT substrate utilizes the halftone mask to implement one photo process, which cannot only accomplish the patterning to the oxide semiconductor layer but also obtain the oxide conductor layer (52?) with ion doping process, and the oxide conductor layer (52?) is employed as being the pixel electrode of the LCD to replace the ITO pixel electrode in prior art; the method manufactures the source (81), the drain (82) and the top gate (71) at the same time with one photo process; the method implements patterning process to the passivation layer (8) and the top gate isolation layer (32) together with one photo process, to reduce the number of the photo processes to five for shortening the manufacture procedure, raising the production efficiency and lowering the production cost.

Abstract: The present invention provides an OLED display device and a manufacturing method thereof, in which a planarization layer (5) of a white sub pixel zone (40) is made to have a thickness greater than the thickness of a planarization layer (5) of the other sub pixel zones so as to increase the vertical distance between bottom wiring (2) and a first electrode (6) in the white sub pixel zone (40) thereby compensating the problem that the vertical distance between the bottom wiring (2) and the first electrode (6) of the white sub pixel zone (40) is relatively small resulting from lacking of a filter in the white sub pixel zone (40) and preventing the occurrence of shorting or over current between the first electrode (6) and the bottom wiring (2) of the white sub pixel zone (40).

Abstract: The present invention provides a TFT backplate structure and a manufacture method thereof. The TFT backplate structure comprises a switch TFT (T1) and a drive TFT (T2). The switch TFT (T1) is constructed by a first source/a first drain (61), a first gate (21), and a first etching stopper layer (51), a first semiconductor layer (41), a first gate isolation layer (31) sandwiched in between. The drive TFT (T2) is constructed by a second source/a second drain (62), a second gate (22), and a second etching stopper layer (52), a second semiconductor layer (42), a second gate isolation layer (32) sandwiched in between. The materials or the thicknesses of the first gate isolation layer (31) and the second gate isolation layer (32) are different. Accordingly, the electrical properties of the switch TFT (T1) and the drive TFT (T2) are different.

Abstract: The present invention provides a TFT backplate structure and a manufacture method thereof. The TFT backplate structure comprises a switch TFT (T1) and a drive TFT (T2). The switch TFT (T1) is constructed by a first source/a first drain (61), a first gate (21), and a first etching stopper layer (51), a first oxide semiconductor layer (41), a first gate isolation layer (31) sandwiched in between. The drive TFT (T2) is constructed by a second source/a second drain (62), a second gate (22), and a second oxide semiconductor layer (42), a first etching stopper layer (51), a second gate isolation layer (32) sandwiched in between. The electrical properties of the switch TFT (T1) and the drive TFT (T2) are different. The switch TFT has smaller subthreshold swing to achieve fast charge and discharge, and the drive TFT has relatively larger subthreshold swing for controlling the current and the grey scale more precisely.

Abstract: The present invention provides a method for manufacturing a TFT substrate having storage capacitors and the TFT substrate.

Abstract: The present invention provides a manufacture method of a thin film transistor backplane, comprising steps of: providing a substrate (20) with a gate (21), an insulation layer (22) and a semiconducting layer (23); sequentially forming a second metal layer, a reflecting electrode layer and a conductive oxide layer on the substrate (20); implementing one photolithographic process to the second metal layer, the reflecting electrode layer and the conductive oxide layer to pattern the second metal layer, the reflecting electrode layer and the conductive oxide layer for respectively forming a source/a drain (253), a reflecting electrode (252) and a pixel electrode (251), and the source/the drain (253) are connected to the semiconducting layer (23; forming a protective layer on the source/the drain (253), the reflecting electrode (252) and the pixel electrode (251; forming a flat and pixel defining layer (27) on the protective layer (26); forming a photospacer (28) on the flat and pixel defining layer (27).

Abstract: The present invention provides a manufacture method and a structure of an oxide thin film transistor. The manufacture method of the structure of the oxide thin film transistor comprises providing a carrier; forming an oxide semiconducting layer (4); forming an etching stopper layer (5); forming two vias (51, 53) in the etching stopper layer (5) to expose the oxide semiconducting layer (4); removing a skin layer of the oxide semiconducting layer (4) in the two vias (51, 53) to form two recesses (41, 43) respectively connecting the two vias (51, 53); forming a source (61) and a drain (63) on the etching stopper layer (5), and the source (61) fills one via (51) and the recess (41) connecting therewith, and the drain (63) fills the other via (53) and the recess (43) connecting therewith; performing a post process.

Abstract: The present invention provides an OLED display device and a manufacturing method thereof, in which a planarization layer (5) of a white sub pixel zone (40) is made to have a thickness greater than the thickness of a planarization layer (5) of the other sub pixel zones so as to increase the vertical distance between bottom wiring (2) and a first electrode (6) in the white sub pixel zone (40) thereby compensating the problem that the vertical distance between the bottom wiring (2) and the first electrode (6) of the white sub pixel zone (40) is relatively small resulting from lacking of a filter in the white sub pixel zone (40) and preventing the occurrence of shorting or over current between the first electrode (6) and the bottom wiring (2) of the white sub pixel zone (40).

Abstract: Disclosed is a thin-film transistor. The thin-film transistor includes: a substrate; a first gate, a first gate insulation layer, a semiconductor layer, an etching stop layer, and the second gate stacked on a surface of the substrate, in which the semiconductor layer has a thickness of 200 nm-2000 nm; the etching stop layer includes a first via and a second via formed therein; and the first via and the second via are arranged to each correspond to the semiconductor layer; and a source and a drain respectively extending through the first via and the second via to connect to the semiconductor layer. The thin-film transistor has an increased ON-state current and switching speed.

Abstract: The present invention provides a method for manufacturing a coplanar oxide semiconductor TFT substrate, which includes: step 1: providing a substrate (1); step 2: forming a gate terminal (2); step 3: depositing a gate insulation layer (3); step 4: forming a photoresist layer (4) on the gate insulation layer (3); step 5: subjecting the photoresist layer (4) to sectionized exposure and development to form a through hole (41) and a plurality of recesses (42); step 6: removing a portion of the gate insulation layer (3) under the through hole (41); step 7: removing portions of the photoresist layer (4) under the plurality of recesses (42) of the photoresist layer (4); step 8: depositing a second metal layer (5) on the gate insulation layer (3) and a remaining photoresist layer (4?); step 9: removing the remaining photoresist layer (4?) and a portion of the second metal layer (5) deposited thereon to form source/drain terminals (51); Step 10: depositing and patternizing an oxide semiconductor layer (6); and step 11