Patents by Inventor Helmut Hagleitner
Helmut Hagleitner has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10367074Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device including a Group III-V semiconductor layer on a surface on a silicon carbide substrate, wherein the semiconductor device defines at least one via through the silicon carbide substrate and the epitaxial layer.Type: GrantFiled: September 26, 2016Date of Patent: July 30, 2019Assignee: Cree, Inc.Inventors: Zoltan Ring, Scott Thomas Sheppard, Helmut Hagleitner
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Patent number: 10090394Abstract: Embodiments of an ohmic contact structure for a Group III nitride semiconductor device and methods of fabrication thereof are disclosed. In general, the ohmic contact structure has a root-mean-squared (RMS) surface roughness of less than 10 nanometers, and more preferably less than or equal to 7.5 nanometers, and more preferably less than or equal to 5 nanometers, and more preferably less than or equal to 2 nanometers, and even more preferably less than or equal to 1.5 nanometers.Type: GrantFiled: November 28, 2016Date of Patent: October 2, 2018Assignee: Cree, Inc.Inventors: Helmut Hagleitner, Jason Gurganus
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Patent number: 10020244Abstract: The present disclosure relates to providing via plugs in vias of a semiconductor material. The via plugs may be formed of a polymer, such as a polyimide, that can withstand subsequent soldering and operating temperatures. The via plugs effectively fill the vias to prevent the vias from being filled substantially with solder during a subsequent soldering processes.Type: GrantFiled: March 27, 2012Date of Patent: July 10, 2018Assignee: Cree, Inc.Inventors: Van Mieczkowski, Helmut Hagleitner, William T. Pulz
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Patent number: 9812338Abstract: Embodiments of a multi-layer environmental barrier for a semiconductor device and methods of manufacturing the same are disclosed. In one embodiment, a semiconductor device is formed on a semiconductor die. The semiconductor die includes a semiconductor body and a passivation structure on the semiconductor body. A multi-level environmental barrier is provided on the passivation structure. The multi-layer environmental barrier is a low-defect multi-layer dielectric film that hermetically seals the semiconductor device from the environment. In one embodiment, the multi-layer environmental barrier has a defect density of less than 10 defects per square centimeter (cm2). By having a low defect density, the multi-layer environmental barrier serves as a robust barrier to the environment.Type: GrantFiled: March 14, 2013Date of Patent: November 7, 2017Assignee: Cree, Inc.Inventors: Zoltan Ring, Helmut Hagleitner, Daniel Namishia
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Patent number: 9640627Abstract: The present disclosure relates to a Schottky contact for a semiconductor device. The semiconductor device has a body formed from one or more epitaxial layers, which reside over a substrate. The Schottky contact may include a Schottky layer, a first diffusion barrier layer, and a third layer. The Schottky layer is formed of a first metal and is provided over at least a portion of a first surface of the body. The first diffusion barrier layer is formed of a silicide of the first metal and is provided over the Schottky layer. The third layer is formed of a second metal and is provided over the first diffusion barrier layer. In one embodiment, the first metal is nickel, and as such, the silicide is nickel silicide. Various other layers may be provided between or above the Schottky layer, the first diffusion barrier layer, and the third layer.Type: GrantFiled: March 7, 2012Date of Patent: May 2, 2017Assignee: Cree, Inc.Inventors: Helmut Hagleitner, Saptharishi Sriram
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Patent number: 9640623Abstract: A transistor device includes a semiconductor body, a spacer layer, and a field plate. The spacer layer is over at least a portion of a surface of the semiconductor body. The field plate is over at least a portion of the spacer layer, and includes a semiconductor layer between a first refractory metal interposer layer and a second refractory metal interposer layer. By including the semiconductor layer between the first refractory metal interposer layer and the second refractory metal interposer layer, the electromigration of metals in the field plate is significantly reduced. Since electromigration of metals in the field plate is a common cause of transistor device failures, reducing the electromigration of metals in the field plate improves the reliability and lifetime of the transistor device.Type: GrantFiled: October 17, 2014Date of Patent: May 2, 2017Assignee: Cree, Inc.Inventor: Helmut Hagleitner
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Patent number: 9607955Abstract: The present disclosure relates to forming multi-layered contact pads for a semiconductor device, wherein the various layers of the contact pad are formed using one or more thin-film deposition processes, such as an evaporation process. Each contact pad includes an adhesion layer, which is formed over the device structure for the semiconductor device; a titanium nitride (TiN) barrier layer, which is formed over the adhesion layer; and an overlay layer, which is formed over the barrier layer. At least the titanium nitride (TiN) barrier layer is formed using an evaporation process.Type: GrantFiled: November 10, 2010Date of Patent: March 28, 2017Assignee: Cree, Inc.Inventors: Van Mieczkowski, Zoltan Ring, Jason Gurganus, Helmut Hagleitner
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Patent number: 9608078Abstract: A transistor device includes a semiconductor body, a spacer layer, and a field plate. The spacer layer is over at least a portion of a surface of the semiconductor body. The field plate is over at least a portion of the spacer layer, and includes a first current carrying layer, a refractory metal interposer layer over the first current carrying layer, and a second current carrying layer over the refractory metal interposer layer. By including the refractory metal interposer layer between the first current carrying layer and the second current carrying layer, the electromigration of metals in the field plate is significantly reduced. Since electromigration of metals in the field plate is a common cause of transistor device failures, reducing the electromigration of metals in the field plate improves the reliability and lifetime of the transistor device.Type: GrantFiled: October 17, 2014Date of Patent: March 28, 2017Assignee: Cree, Inc.Inventors: Helmut Hagleitner, Fabian Radulescu, Saptharishi Sriram, Daniel Etter
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Publication number: 20170077254Abstract: Embodiments of an ohmic contact structure for a Group III nitride semiconductor device and methods of fabrication thereof are disclosed. In general, the ohmic contact structure has a root-mean-squared (RMS) surface roughness of less than 10 nanometers, and more preferably less than or equal to 7.5 nanometers, and more preferably less than or equal to 5 nanometers, and more preferably less than or equal to 2 nanometers, and even more preferably less than or equal to 1.5 nanometers.Type: ApplicationFiled: November 28, 2016Publication date: March 16, 2017Inventors: Helmut Hagleitner, Jason Gurganus
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Patent number: 9548206Abstract: Embodiments of an ohmic contact structure for a Group III nitride semiconductor device and methods of fabrication thereof are disclosed. In general, the ohmic contact structure has a root-mean-squared (RMS) surface roughness of less than 10 nanometers, and more preferably less than or equal to 7.5 nanometers, and more preferably less than or equal to 5 nanometers, and more preferably less than or equal to 2 nanometers, and even more preferably less than or equal to 1.5 nanometers.Type: GrantFiled: July 14, 2011Date of Patent: January 17, 2017Assignee: Cree, Inc.Inventors: Helmut Hagleitner, Jason Gurganus
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Publication number: 20170012106Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device including a Group III-V semiconductor layer on a surface on a silicon carbide substrate, wherein the semiconductor device defines at least one via through the silicon carbide substrate and the epitaxial layer.Type: ApplicationFiled: September 26, 2016Publication date: January 12, 2017Inventors: Zoltan Ring, Scott Thomas Sheppard, Helmut Hagleitner
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Patent number: 9536783Abstract: Embodiments of a semiconductor wafer having wafer-level die attach metallization on a back-side of the semiconductor wafer, resulting semiconductor dies, and methods of manufacturing the same are disclosed. In one embodiment, a semiconductor wafer includes a semiconductor structure and a front-side metallization that includes front-side metallization elements for a number of semiconductor die areas. The semiconductor wafer also includes vias that extend from a back-side of the semiconductor structure to the front-side metallization elements. A back-side metallization is on the back-side of the semiconductor structure and within the vias. For each via, one or more barrier layers are on a portion of the back-side metallization that is within the via and around a periphery of the via. The semiconductor wafer further includes wafer-level die attach metallization on the back-side metallization other than the portions of the back-side metallization that are within the vias and around the peripheries of the vias.Type: GrantFiled: January 7, 2015Date of Patent: January 3, 2017Assignee: Cree, Inc.Inventors: Fabian Radulescu, Helmut Hagleitner, Terry Alcorn, William T. Pulz, Van Mieczkowski
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Patent number: 9490169Abstract: A method of fabricating an integrated circuit on a silicon carbide substrate is disclosed that eliminates wire bonding that can otherwise cause undesired inductance. The method includes fabricating a semiconductor device including a Group III-V semiconductor layer on a surface on a silicon carbide substrate, wherein the semiconductor device defines at least one via through the silicon carbide substrate and the epitaxial layer.Type: GrantFiled: November 2, 2010Date of Patent: November 8, 2016Assignee: Cree, Inc.Inventors: Zoltan Ring, Scott Thomas Sheppard, Helmut Hagleitner
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Patent number: 9343543Abstract: Embodiments of a gate contact for a semiconductor device and methods of fabrication thereof are disclosed. In one embodiment, a semiconductor device includes a semiconductor structure and a dielectric layer on a surface of the semiconductor structure, where the dielectric layer has an opening that exposes an area of the semiconductor structure. A gate contact for the semiconductor device is formed on the exposed area of the semiconductor structure through the opening in the dielectric layer. The gate contact includes a proximal end on a portion of the exposed area of the semiconductor structure, a distal end opposite the proximal end, and sidewalls that each extend between the proximal end and the distal end of the gate contact. For each sidewall of the gate contact, an air region separates the sidewall and the distal end of the gate contact from the dielectric layer.Type: GrantFiled: January 23, 2015Date of Patent: May 17, 2016Assignee: Cree, Inc.Inventors: Fabian Radulescu, Helmut Hagleitner
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Publication number: 20160111502Abstract: A transistor device includes a semiconductor body, a spacer layer, and a field plate. The spacer layer is over at least a portion of a surface of the semiconductor body. The field plate is over at least a portion of the spacer layer, and includes a semiconductor layer between a first refractory metal interposer layer and a second refractory metal interposer layer. By including the semiconductor layer between the first refractory metal interposer layer and the second refractory metal interposer layer, the electromigration of metals in the field plate is significantly reduced. Since electromigration of metals in the field plate is a common cause of transistor device failures, reducing the electromigration of metals in the field plate improves the reliability and lifetime of the transistor device.Type: ApplicationFiled: October 17, 2014Publication date: April 21, 2016Inventor: Helmut Hagleitner
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Publication number: 20160111503Abstract: A transistor device includes a semiconductor body, a spacer layer, and a field plate. The spacer layer is over at least a portion of a surface of the semiconductor body. The field plate is over at least a portion of the spacer layer, and includes a first current carrying layer, a refractory metal interposer layer over the first current carrying layer, and a second current carrying layer over the refractory metal interposer layer. By including the refractory metal interposer layer between the first current carrying layer and the second current carrying layer, the electromigration of metals in the field plate is significantly reduced. Since electromigration of metals in the field plate is a common cause of transistor device failures, reducing the electromigration of metals in the field plate improves the reliability and lifetime of the transistor device.Type: ApplicationFiled: October 17, 2014Publication date: April 21, 2016Inventors: Helmut Hagleitner, Fabian Radulescu, Saptharishi Sriram, Daniel Etter
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Patent number: 9269662Abstract: A semiconductor die, which includes a substrate, a group of primary conduction sub-layers, and a group of separation sub-layers, is disclosed. The group of primary conduction sub-layers is over the substrate. Each adjacent pair of the group of primary conduction sub-layers is separated by at least one of the group of separation sub-layers. As a result, the group of separation sub-layers mitigates grain growth in the group of primary conduction sub-layers.Type: GrantFiled: October 17, 2012Date of Patent: February 23, 2016Assignee: Cree, Inc.Inventors: Zoltan Ring, Helmut Hagleitner, Daniel Namishia, Fabian Radulescu
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Publication number: 20150364569Abstract: Embodiments of a gate contact for a semiconductor device and methods of fabrication thereof are disclosed. In one embodiment, a semiconductor device includes a semiconductor structure and a dielectric layer on a surface of the semiconductor structure, where the dielectric layer has an opening that exposes an area of the semiconductor structure. A gate contact for the semiconductor device is formed on the exposed area of the semiconductor structure through the opening in the dielectric layer. The gate contact includes a proximal end on a portion of the exposed area of the semiconductor structure, a distal end opposite the proximal end, and sidewalls that each extend between the proximal end and the distal end of the gate contact. For each sidewall of the gate contact, an air region separates the sidewall and the distal end of the gate contact from the dielectric layer.Type: ApplicationFiled: January 23, 2015Publication date: December 17, 2015Inventors: Fabian Radulescu, Helmut Hagleitner
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Patent number: 9214352Abstract: Embodiments of an ohmic contact structure for a Group III nitride semiconductor device and methods of fabrication thereof are disclosed. In one embodiment, the ohmic contact structure has less than or equal to 5%, more preferably less than or equal to 2%, more preferably less than or equal to 1.5%, and even more preferably less than or equal to 1% degradation for 1000 hours High Temperature Soak (HTS) at 300 degrees Celsius. In another embodiment, the ohmic contact structure additionally or alternatively has less than or equal to 10% degradation, more preferably less than or equal to 7.5% degradation, more preferably less than or equal to 6% degradation, more preferably less than or equal to 5% degradation, and even more preferably less than 3% degradation for 1000 hours High Temperature operating Life (HToL) at 225 degrees Celsius and 50 milliamps (mA) per millimeter (mm).Type: GrantFiled: July 14, 2011Date of Patent: December 15, 2015Assignee: Cree, Inc.Inventors: Helmut Hagleitner, Daniel Namishia
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Patent number: 9202703Abstract: Embodiments of a Nickel-rich (Ni-rich) Schottky contact for a semiconductor device and a method of fabrication thereof are disclosed. Preferably, the semiconductor device is a radio frequency or power device such as, for example, a High Electron Mobility Transistor (HEMT), a Schottky diode, a Metal Semiconductor Field Effect Transistor (MESFET), or the like. In one embodiment, the semiconductor device includes a semiconductor body and a Ni-rich Schottky contact on a surface of the semiconductor body. The Ni-rich Schottky contact includes a multilayer Ni-rich contact metal stack. The semiconductor body is preferably formed in a Group III nitride material system (e.g., includes one or more Gallium Nitride (GaN) and/or Aluminum Gallium Nitride (AlGaN) layers). Because the Schottky contact is Ni-rich, leakage through the Schottky contact is substantially reduced.Type: GrantFiled: November 5, 2012Date of Patent: December 1, 2015Assignee: Cree, Inc.Inventors: Helmut Hagleitner, Fabian Radulescu, Daniel Namishia