Patents by Inventor Helmut Strack
Helmut Strack has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 6309974Abstract: Residual oxygen impurities are eliminated from silicon wafers pulled from a crucible (Czochralski silicon). A multitude of trenches are etched into the back side of the crucible-pulled silicon wafer and the wafer is subsequently heat-treated at about 1100° C. The very large surface area at the front side of the silicon wafer allows oxygen impurities to diffuse out effectively. After the diffusion has been carried out, the trenches are filled with heavily doped polysilicon without leaving gaps.Type: GrantFiled: September 17, 1998Date of Patent: October 30, 2001Assignee: Infineon Technologies AGInventors: Helmut Strack, Jens-Peer Stengl
-
Publication number: 20010005036Abstract: A power semiconductor components has stop zones. In order to optimize the static and dynamic losses of the power semiconductor components, the stop zone is provided with donors which have at least one donor level which lies within the band gap of silicon and is at least 200 meV away from the conduction band edge of silicon.Type: ApplicationFiled: January 17, 2001Publication date: June 28, 2001Inventors: Alfred Porst, Helmut Strack, Anton Mauder, Hans-Joachim Schulze, Heinrich Brunner, Josef Bauer, Reiner Barthelmess
-
Patent number: 6248620Abstract: A method for fabricating field effect-controlled semiconductor components, such as e.g. but not exclusively MIS power transistors. The field effect-controllable semiconductor component has a semiconductor substrate of a first conductivity type and a gate insulator layer on the surface of the semiconductor substrate. A well of a second conductivity type is produced in the semiconductor substrate by implanting first impurity atoms. A semiconductor layer having a first predetermined thickness is produced on the gate insulator layer prior to the production of the well. The semiconductor layer is reduced in a predtdermined region to obtain a residual layer having a second predetermined thickness, such that the semiconductor layer acts as an implantation barrier outside the predetermined region when the well is produced.Type: GrantFiled: January 24, 2000Date of Patent: June 19, 2001Assignee: Infineon Technologies AGInventors: Helmut Strack, Helmut Gassel, Joost Larik
-
Patent number: 6225643Abstract: An SOI cell includes a semiconductor body having at least one insulator layer. A polycrystalline zone doped with a dopant of a first conductivity type is grown on the insulator layer. The polycrystalline zone is adjoined outside the region of the insulator layer by a semiconductor region, which is doped with the dopant of the first conduction type that has been diffused out of the polycrystalline zone. A dopant source having a dopant of a second conductivity type is also provided. A zone having the dopant of the second conductivity type is formed by diffusing the dopant out of the dopant source.Type: GrantFiled: September 22, 1998Date of Patent: May 1, 2001Assignee: Infineon Technologies AGInventors: Jenoe Tihanyi, Helmut Strack
-
Patent number: 6184555Abstract: The invention relates to a field effect-controllable semiconductor component of vertical or lateral design i.e. MOSFETs and IGBTs. In this case, depletion zones and complementary depletion zones of opposite conduction types are introduced in the source-drain load path, in the semiconductor body, i.e. in the inner zone in the case of vertical components and in the drift zone in the case of lateral components, the concentration of the regions doped by the first conduction type corresponding approximately to the concentration of the regions doped by the second conduction type.Type: GrantFiled: December 4, 1998Date of Patent: February 6, 2001Assignee: Siemens AktiengesellschaftInventors: Jeno Tihanyi, Helmut Strack, Heinrich Geiger
-
Patent number: 6072220Abstract: A semiconductor body includes a lightly doped semiconductor zone of a second conductivity type. A first oxide layer is produced on the semiconductor body. A structured polysilicon layer is produced on the oxide layer. The polysilicon layer acts as a mask so that the dopants of one conductivity type are implanted and driven into the surface of the semiconductor zone. A second oxide layer is then produced on the surface of the polysilicon layer and the semiconductor zone. A spacer is etched from this oxide layer. Dopants of the second conductivity type are implanted and driven into the surface of the semiconductor zone. A narrow resistor zone remains lying under the polysilicon layer.Type: GrantFiled: December 7, 1998Date of Patent: June 6, 2000Assignee: Siemens AktiengesellschaftInventor: Helmut Strack
-
Patent number: 6063684Abstract: In a method for eliminating residual oxygen contaminations from crucible-drawn silicon wafers, a number of trenches are etched into the front side of a crucible-drawn silicon wafer and that the silicon wafer is subsequently tempered at approximately 1100.degree. C. As a result of the extremely large surface area in the front side of the silicon wafer, oxygen contaminants can effectively diffuse out. After the oxygen drive-out has ensued, the trenches are filled bubble-free with epitaxially deposited silicon and the active structures are processed into the front side.Type: GrantFiled: September 4, 1998Date of Patent: May 16, 2000Assignee: Siemens AktiengesellschaftInventor: Helmut Strack
-
Patent number: 5583060Abstract: The base zones of MOSFETs and IGBTs are generated by implanting dopants of the second conductivity type into the surface of a first layer of the first conductivity type, and a second layer of the first conductivity type is deposited thereon. During the deposition, the dopants diffuse up to the surface of the second layer and form base zones. The base zones are thereby provided with a laterally expanded region of high conductivity under the surface through which the minority carriers can flow off to the source electrode with low voltage drop.Type: GrantFiled: November 3, 1995Date of Patent: December 10, 1996Assignee: Siemens AktiengesellschaftInventors: Helmut Hertrich, Helmut Strack, Jenoe Tihanyi
-
Patent number: 5396088Abstract: The source zone of an MOS component on a semiconductor body is disposed on the upper side of the gate electrode, and is in contact at an upper side of the source zone, with a source electrode. The base zone laterally adjoins the source zone and laterally adjoins the gate electrode at the drain zone. The minority charge carriers which flow from the semiconductor body to the cathode therefore flow directly to the source electrode through that part of the base zone disposed next to the gate electrode. An activation of a parasitic bipolar transistor, and thus the occurrence of so-called second breakdown, are thus avoided.Type: GrantFiled: May 10, 1994Date of Patent: March 7, 1995Assignee: Siemens AktiengesellschaftInventor: Helmut Strack
-
Patent number: 5311052Abstract: Semiconductor component, including a semiconductor body having an edge, a surface, a substrate of a first given conductivity type, at least one zone being embedded in a planar manner in the substrate at the surface and being of a second conductivity type opposite the first given type, and insulating layer disposed on the surface, an electrode being in contact with the at least one zone, a channel stopper disposed on the insulating layer outside the at least one zone and in vicinity of the edge of the semiconductor body, the channel stopper being electrically connected to the substrate, and a field plate beind disposed on the insulating layer between the at least one zone and the channel stopper and being electrically connected to the at least one zone, the channel stopper being disposed at an increasing distance from the edge and the surface of the semiconductor body, as seen in direction toward the at least one zone.Type: GrantFiled: September 29, 1982Date of Patent: May 10, 1994Assignee: Siemens AktiengesellschaftInventors: Jens P. Stengl, Helmut Strack, Jeno Tihanyi
-
Patent number: 5302537Abstract: A manufacturing method for a low-voltage power MISFET which utilizes only three masks (photosteps). In the first step, a polysilicon layer (3) is structured and a cell field and edge zones are produced. An oxide layer (2) is then applied, this being opened in the second photostep above the cells and the edge zones and between the edge (4) and the cells. A metal layer is then applied, this being interrupted between the cells and the edge (4) with the third photostep. Field plates and a channel stopper (9) are thus produced. As last step, a weakly conductive layer (20) is applied onto the entire surface.Type: GrantFiled: November 13, 1992Date of Patent: April 12, 1994Assignee: Siemens AktiengesellschaftInventor: Helmut Strack
-
Patent number: 5087577Abstract: A manufacturing method for a low-voltage power MISFET which utilizes three maskes (photosteps) is provided. In the first step, a polysilicon layer is structured and a cell field and edge zones are manufactured. An oxide layer is then applied, this being opened in the second photostep above the cells and the edge zones and between the edge and the cells. A metal layer is then applied, this being interrupted between the cells and the edge zones with the third photostep. Field plates and a channel stopper are thus produced.Type: GrantFiled: June 5, 1991Date of Patent: February 11, 1992Assignee: Siemens AktiengesellschaftInventor: Helmut Strack
-
Patent number: 4903112Abstract: A semiconductor component. The semiconductor component has two superimposed semiconductor layers of different conduction materials. An upper layer is provided with an opening through which a lower layer is exposed. A space saving scheme for connecting electrically the two layers is provided, by depositing a connecting layer which contacts the upper layer at an edge only and the lower layer is contacted at its depth where its doping material maximum is located. This requires a doping equal to or greater than 10.sup.19 cm.sup.-3 for the upper layer, which is dependent on thickness.Type: GrantFiled: June 22, 1988Date of Patent: February 20, 1990Assignee: Siemens AktiengesellschaftInventors: Helmut Strack, Gottfried Schuh
-
Patent number: 4893165Abstract: A field effect controllable bipolar transistor or isolated gate bipolar transistor (IGBT) has a drastically reduced inhibit delay charge, given identical on-state behavior, in that the anode zone has a thickness of less that 1 micrometer, it is doped with implanted ions with a dose of about 1.times.10.sup.12 through 1.times.10.sup.15 cm.sup.-2, and in that the life time of the minority charge carriers in the inner zone amounts to at least 1 microsecond.Type: GrantFiled: February 21, 1989Date of Patent: January 9, 1990Assignee: Siemens AktiengesellschaftInventors: Gerhard Miller, Helmut Strack, Jenoe Tihanyi
-
Patent number: 4792839Abstract: A semiconductor power circuit breaker has several emitter zones of a width (b) less than 30 microns. The semiconductor device may be in the form of a switching transistor or a gate turn off (GTO) thyristor. The spacing (a) of the emitter zones is less than the thickness (d) of the low doped inner zone. The power circuit breaker can thus be operated up to the collector-base break-down voltage U.sub.CBO without a destruction through "second break-down" occurring. On the other hand, high current carrying capacity is maintained, since it depends practically only on the chip surface instead of being a function of emitter area.Type: GrantFiled: December 21, 1987Date of Patent: December 20, 1988Assignee: Siemens AktiengesellschaftInventors: Helmut Strack, Helmut Herberg
-
Patent number: 4760432Abstract: A thyristor having a pnpn semiconductor body comprising MISFET structures 9 and 12 through 16 which serve as controllable emitter base shorts formed at the edge side relative to one of the emitter layers and each of the structures is composed of a semiconductor region 9 inserted into the emitter layer which is contacted by an electrode 6 for the emitter layer 1 and also includes a subregion 12 of the adjacent base layer 2 and of an intervening channel region 13 which is formed of an edge zone of the emitter layer 1 and is also composed of a gate covering the channel region in an insulated manner. The gate also convers the subregion 12 of the base layer 2 and forms a MIS capacitor C1. A voltage generator 23 drives the gate 15 with a voltage which alternates between first and second values.Type: GrantFiled: October 28, 1986Date of Patent: July 26, 1988Assignee: Siemens AktiengesellschaftInventors: Michael Stoisiek, Horst Schmid, Helmut Strack
-
Patent number: 4612448Abstract: Connected in series with a thyristor (1) are two IGFETs (2, 3) one to the anode side and the other to the cathode side. Between the inner thyristor zones (6, 8) and the outer IGFET connections, a threshold circuit (10, 11) is connected to each. The threshold voltage of the threshold circuit is higher than that of the p-n junctions between the outer and adjacent inner thyristor zones (6, 7; 8, 9) including the voltage drop of the conducting IGFET. The switch is turned off by operating to turn off the IGFETs. The current then flows via the threshold elements through the two inner zones (6, 8). The charge carriers of this diode are evacuated very quickly, since carrier injection from the outer zones is no longer possible.Type: GrantFiled: February 4, 1985Date of Patent: September 16, 1986Assignee: Siemens AktiengesellschaftInventor: Helmut Strack
-
Patent number: 4543596Abstract: An IGFET assembly, includes a semiconductor substrate of a given first conductivity type having first and second surfaces, an IGFET having at least one channel zone of a second conductivity type opposite the first given conductivity type embedded in the first surface of the substrate, a source zone of the first conductivity type embedded planar in the channel zone, a drain zone adjacent the first surface of the substrate, a drain electrode connected to the second surface of the substrate, an insulating layer disposed on the first surface of the substrate, at least one gate electrode disposed on the insulating layer, at least one injector zone of the second conductivity type embedded in the first surface of the substrate, a contact for connecting the injector zone to a voltage source, an emitter zone of the first conductivity type embedded in the injector zone, the emitter zone having a heavier doping than the injector zone, the injector zone including a part thereof emerging to the first surface of the substrType: GrantFiled: June 30, 1983Date of Patent: September 24, 1985Assignee: Siemens AktiengesellschaftInventors: Helmut Strack, Jeno Tihanyi
-
Patent number: 4079406Abstract: A thyristor device is provided with a shorted emitter structure in which the shorts are circularly formed zones of the base zone which extend through the emitter zone into electrical contact with the emitter electrode. Each of these zones is circular in cross-section and of a diameter which is less than 20.mu.m. These zones have a spacing from each other from center to center which is such that the ratio of this spacing to the diameter of a circular area is greater than 3.Type: GrantFiled: December 9, 1976Date of Patent: March 14, 1978Assignee: Siemens AktiengesellschaftInventors: Joachim Burtscher, Helmut Strack