Patents by Inventor Hem Takiar

Hem Takiar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • SEMICONDUCTOR PACKAGE INCLUDING FLIP CHIP CONTROLLER AT BOTTOM OF DIE STACK
    Publication number: 20090166887
    Abstract: A semiconductor package including a plurality of stacked semiconductor die, and methods of forming the semiconductor package, are disclosed. In order to ease wirebonding requirements on the controller die, the controller die may be mounted directly to the substrate in a flip chip arrangement requiring no wire bonds or footprint outside of the controller die. Thereafter, a spacer layer may be affixed to the substrate around the controller die to provide a level surface on which to mount one or more flash memory die. The spacer layer may be provided in a variety of different configurations.
    Type: Application
    Filed: December 27, 2007
    Publication date: July 2, 2009
    Inventors: Suresh Upadhyayula, Hem Takiar
  • Stacked, interconnected semiconductor packages
    Patent number: 7550834
    Abstract: An electronic component is disclosed including a plurality of stacked semiconductor packages. A first such embodiment includes an internal connector for electrically coupling the stacked semiconductor packages. A second such embodiment includes an external connector for electrically coupling the stacked semiconductor packages.
    Type: Grant
    Filed: June 29, 2006
    Date of Patent: June 23, 2009
    Assignee: SanDisk Corporation
    Inventors: Cheemen Yu, Chih-Chin Liao, Hem Takiar
  • LEADFRAME BASED FLASH MEMORY CARDS
    Publication number: 20090134502
    Abstract: A leadframe design for forming leadframe-based semiconductor packages having curvilinear shapes is disclosed. The leadframes may each include one or more curvilinear slots corresponding to curvilinear edges in the finished and singulated semiconductor package. After encapsulation, the integrated circuit packages on the panel may be singulated by cutting the integrated circuits from the leadframe panel into a plurality of individual integrated circuit packages. The slots in the leadframe advantageously allow each leadframe to be singulated using a saw blade making only straight cuts.
    Type: Application
    Filed: January 30, 2009
    Publication date: May 28, 2009
    Applicant: SANDISK CORPORATION
    Inventors: Hem Takiar, Shrikar Bhagath
  • METHOD OF REDUCING MEMORY CARD EDGE ROUGHNESS BY EDGE COATING
    Publication number: 20090085232
    Abstract: A method of forming a semiconductor package with smooth edges, and a semiconductor package formed thereby is disclosed. In embodiments, after encapsulation, the semiconductor packages may be at least partially singulated from the panel by making one or more cuts through the panel to define one or more edges of the semiconductor package. The one or more edges may be smoothed by applying a laminate to the edges. The edges receiving the laminate may include any edge between a top and bottom surface of the package.
    Type: Application
    Filed: September 28, 2007
    Publication date: April 2, 2009
    Inventors: Ong King Hoo, Java Zhu, Ning Ye, Hem Takiar
  • METHOD OF REDUCING MEMORY CARD EDGE ROUGHNESS BY PARTICLE BLASTING
    Publication number: 20090085231
    Abstract: A method of forming a semiconductor package with smooth edges, and a semiconductor package formed thereby is disclosed. In embodiments, after encapsulation, a panel of semiconductor packages may undergo a first cutting process which cuts the curvilinear edges of the packages. Next, the partially singulated panel of packages may undergo an abrasion process for smoothing the cut curvilinear edges. The abrasion process may occur by forcing abrasive particles over the jagged side edges of a semiconductor package as a result of a pressure differential above and below the semiconductor packages. Upon completion of the abrasive process, a second cutting process may be performed which cuts along straight edges and singulates the respective packages from the panel.
    Type: Application
    Filed: September 28, 2007
    Publication date: April 2, 2009
    Inventors: Chin-Tien Chiu, Chih Chiang Tung, Hem Takiar, Jack Chang Chien, Cheemen Yu
  • METHOD OF FORMING A SEMICONDUCTOR DIE HAVING A SLOPED EDGE FOR RECEIVING AN ELECTRICAL CONNECTOR
    Publication number: 20090065902
    Abstract: A method of forming a low profile semiconductor package, and a semiconductor package formed thereby, is disclosed. The semiconductor die is formed with one or more sloped edges on which electrically conductive traces may be deposited to allow the semiconductor die to be coupled to another die and/or a substrate on which the die is mounted. Depositing the electrical traces directly on the surface and sloped edge of the die allows the die to be electrically coupled without bond wires, thereby allowing a reduction in the overall thickness of the package.
    Type: Application
    Filed: September 11, 2007
    Publication date: March 12, 2009
    Inventors: Cheemen Yu, Chih-Chin Liao, Hem Takiar
  • Test pads on flash memory cards
    Patent number: 7495255
    Abstract: A semiconductor package is disclosed including test pads formed of solder bumps affixed to the semiconductor package during fabrication. When the package is encapsulated, due to the pressure exerted on the package during the encapsulation process, portions of the solder bumps get flattened out to be generally flush with and exposed on a surface of the semiconductor package. These exposed portions of the solder bumps form the test pads by which the finished package may be tested.
    Type: Grant
    Filed: July 12, 2007
    Date of Patent: February 24, 2009
    Assignee: SanDisk Corporation
    Inventors: Hem Takiar, Shrikar Bhagath
  • Method of fabricating leadframe based flash memory cards including singulation by straight line cuts
    Patent number: 7488620
    Abstract: Methods for forming leadframe-based semiconductor packages having curvilinear shapes are disclosed. The leadframes may each include one or more curvilinear slots corresponding to curvilinear edges in the finished and singulated semiconductor package. After encapsulation, the integrated circuit packages on the panel may be singulated by cutting the integrated circuits from the leadframe panel into a plurality of individual integrated circuit packages. The slots in the leadframe advantageously allow each leadframe to be singulated using a saw blade making only straight cuts.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: February 10, 2009
    Assignee: SanDisk Corporation
    Inventors: Hem Takiar, Shrikar Bhagath
  • Method of manufacturing flash memory cards
    Patent number: 7485501
    Abstract: A method is disclosed for forming semiconductor packages by a process of punching and cutting the packages from a panel of integrated circuits. During an encapsulation process for encapsulating the packages in a molding compound, portions of the panel may be left free of molding compound. Portions of the panel left free of molding compound may subsequently be punched from the panel. These punched areas may define chamfers, notches or a variety of other curvilinear, rectilinear or irregular shapes in the outer edges of the finished semiconductor package. After the panel is punched, the integrated circuits may be singulated. By punching areas from the panel, and then cutting along straight edges, a simple, effective and cost efficient method is disclosed for obtaining finished semiconductor packages of a variety of desired shapes.
    Type: Grant
    Filed: November 2, 2005
    Date of Patent: February 3, 2009
    Assignee: SanDisk Corporation
    Inventors: Hem Takiar, Shrikar Bhagath, Chin-Tien Chiu
  • MEMORY CARD FABRICATED USING SIP/SMT HYBRID TECHNOLOGY
    Publication number: 20090001365
    Abstract: A portable memory card formed from a multi-die assembly, and methods of fabricating same, are disclosed. One such multi-die assembly includes an LGA SiP semiconductor package and a leadframe-based SMT package both affixed to a PCB. The multi-die assembly thus formed may be encased within a standard lid to form a completed portable memory card, such as a standard SD™ card. Test pads on the LGA SiP package, used for testing operation of the package after it is fabricated, may also be used for physically and electrically coupling the LGA SiP package to the PCB.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 1, 2009
    Inventors: Ning Ye, Robert C. Miller, Cheemen Yu, Hem Takiar, Andre McKenzie
  • TWO-SIDED DIE IN A FOUR-SIDED LEADFRAME BASED PACKAGE
    Publication number: 20090001534
    Abstract: A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. In embodiments, a semiconductor die having die bond pads along two adjacent edges may be electrically coupled to four sides of a four-sided leadframe. Embodiments relate to lead and no-lead type leadframe.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 1, 2009
    Inventors: Cheemen Yu, Vani Verma, Hem Takiar
  • METHOD OF FABRICATING A SEMICONDUCTOR PACKAGE HAVING THROUGH HOLES FOR MOLDING BACK SIDE OF PACKAGE
    Publication number: 20090004785
    Abstract: A portable memory card and methods of manufacturing same are disclosed. The portable memory includes a substrate having a plurality of holes formed therein. During the encapsulation process, mold compound flows over the top surface of the substrate, through the holes, and down into a recessed section formed in the bottom mold cap plate to form a projection of mold compound on the bottom surface of the substrate.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 1, 2009
    Inventors: Chin-Tien Chiu, Hem Takiar, Chih-Chin Liao, Cheemen Yu, Ning Ye, Jack Chang Chien
  • METHOD OF FABRICATING A SEMICONDUCTOR DIE HAVING A REDISTRIBUTION LAYER
    Publication number: 20090004781
    Abstract: A semiconductor device having a redistribution layer, and methods of forming same, are disclosed. After fabrication of semiconductor die on a wafer, a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer. The tape assembly includes a backgrind tape as a base layer, and a film assembly adhered to the backgrind tape. The film assembly in turn includes an adhesive film on which is deposited a thin layer of conductive material. The redistribution layer pattern is traced into the tape assembly, using for example a laser. Thereafter, the unheated portions of the tape assembly may be removed, leaving the heated redistribution layer pattern on each semiconductor die.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 1, 2009
    Inventors: Chien-Ko Liao, Chin-Tien Chiu, Jack Chang Chien, Cheemen Yu, Hem Takiar
  • METHOD OF FABRICATING A MEMORY CARD USING SIP/SMT HYBRID TECHNOLOGY
    Publication number: 20090004776
    Abstract: A portable memory card formed from a multi-die assembly, and methods of fabricating same, are disclosed. One such multi-die assembly includes an LGA SiP semiconductor package and a leadframe-based SMT package both affixed to a PCB. The multi-die assembly thus formed may be encased within a standard lid to form a completed portable memory card, such as a standard SD™ card. Test pads on the LGA SiP package, used for testing operation of the package after it is fabricated, may also be used for physically and electrically coupling the LGA SiP package to the PCB.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 1, 2009
    Inventors: Ning Ye, Robert C. Miller, Cheemen Yu, Hem Takiar, Andre McKenzie
  • SEMICONDUCTOR DIE HAVING A REDISTRIBUTION LAYER
    Publication number: 20090001610
    Abstract: A semiconductor device having a redistribution layer, and methods of forming same, are disclosed. After fabrication of semiconductor die on a wafer, a tape assembly is applied onto a surface of the wafer, in contact with the surfaces of each semiconductor die on the wafer. The tape assembly includes a backgrind tape as a base layer, and a film assembly adhered to the backgrind tape. The film assembly in turn includes an adhesive film on which is deposited a thin layer of conductive material. The redistribution layer pattern is traced into the tape assembly, using for example a laser. Thereafter, the unheated portions of the tape assembly may be removed, leaving the heated redistribution layer pattern on each semiconductor die.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 1, 2009
    Inventors: Chien-Ko Liao, Chin-Tien Chiu, Jack Chang Chien, Cheemen Yu, Hem Takiar
  • SEMICONDUCTOR PACKAGE HAVING THROUGH HOLES FOR MOLDING BACK SIDE OF PACKAGE
    Publication number: 20090001552
    Abstract: A portable memory card and methods of manufacturing same are disclosed. The portable memory includes a substrate having a plurality of holes formed therein. During the encapsulation process, mold compound flows over the top surface of the substrate, through the holes, and down into a recessed section formed in the bottom mold cap plate to form a projection of mold compound on the bottom surface of the substrate.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 1, 2009
    Inventors: Chin-Tien Chiu, Hem Takiar, Chih-Chin Liao, Cheemen Yu, Ning Ye, Jack Chang Chien
  • METHOD OF FABRICATING A TWO-SIDED DIE IN A FOUR-SIDED LEADFRAME BASED PACKAGE
    Publication number: 20090004782
    Abstract: A method of fabricating a leadframe-based semiconductor package, and a semiconductor package formed thereby, are disclosed. In embodiments, a semiconductor die having die bond pads along two adjacent edges may be electrically coupled to four sides of a four-sided leadframe. Embodiments relate to lead and no-lead type leadframe.
    Type: Application
    Filed: June 28, 2007
    Publication date: January 1, 2009
    Inventors: Cheemen Yu, Vani Verma, Hem Takiar
  • SEMICONDUCTOR MOLDED PANEL HAVING REDUCED WARPAGE
    Publication number: 20080305306
    Abstract: A panel is disclosed on which a plurality of integrated circuit package outlines may be fabricated within a plurality of process tools. The panel includes recessed portions in the exposed surfaces of the molding compound and/or the substrate. The recesses relieve stress resulting from disparate coefficients of expansion between the substrate and molding compound applied to the substrate around the integrated circuits. In embodiments, the recesses may be formed as lines scored into the surface of the molding compound or substrate. Alternatively, the recesses may be formed in the solder mask on the substrate during a process for applying the solder mask, or the recesses may be formed in the molding compound during the encapsulation process.
    Type: Application
    Filed: June 7, 2007
    Publication date: December 11, 2008
    Inventors: Cheemen Yu, Chih-Chin Liao, Hem Takiar
  • METHOD OF MINIMIZING KERF WIDTH ON A SEMICONDUCTOR SUBSTRATE PANEL
    Publication number: 20080305577
    Abstract: A semiconductor die substrate panel is disclosed including a minimum kerf width between adjoining semiconductor package outlines on the panel, while ensuring electrical isolation of plated electrical terminals. By reducing the width of a boundary between adjoining package outlines, additional space is gained on a substrate panel for semiconductor packages.
    Type: Application
    Filed: June 8, 2007
    Publication date: December 11, 2008
    Inventors: Chih-Chin Liao, Ning Ye, Cheemen Yu, Jack Chang Chien, Hem Takiar
  • METHOD OF REDUCING WARPAGE IN SEMICONDUCTOR MOLDED PANEL
    Publication number: 20080305576
    Abstract: A panel is disclosed on which a plurality of integrated circuit package outlines may be fabricated within a plurality of process tools. The panel includes recessed portions in the exposed surfaces of the molding compound and/or the substrate. The recesses relieve stress resulting from disparate coefficients of expansion between the substrate and molding compound applied to the substrate around the integrated circuits. In embodiments, the recesses may be formed as lines scored into the surface of the molding compound or substrate. Alternatively, the recesses may be formed in the solder mask on the substrate during a process for applying the solder mask, or the recesses may be formed in the molding compound during the encapsulation process.
    Type: Application
    Filed: June 7, 2007
    Publication date: December 11, 2008
    Inventors: Cheemen Yu, Chih-Chin Liao, Hem Takiar