Patents by Inventor Hemant Deshpande
Hemant Deshpande has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11555627Abstract: A system is provided and includes a first controller, a non-transitory computer-readable medium and a second controller. The first controller is configured to control operation of at least one compressor circuit including one or more compressors. The non-transitory computer-readable medium is configured to store instructions of a stage profiler for execution by the controller. The instructions include: determining a target system capacity profile for the at least one compressor circuit; determining system stage capacities for stages of the at least one compressor circuit; selecting some of the system stage capacities based on the target system capacity profile to provide an available system capacity profile; generating modulation information based on the available system capacity profile and a load request signal; and controlling operation of the one or more compressors based on the modulation information and according to the available system capacity profile.Type: GrantFiled: July 12, 2018Date of Patent: January 17, 2023Assignee: Emerson Climate Technologies, Inc.Inventors: Richard Evans Speaker, Chetan Avinash Sowani, Kamalakkannan Muthusubramanian, Tanmay Hemant Deshpande
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Patent number: 11321717Abstract: An account holder's portfolio of transactions may be represented as a network of interconnected transaction nodes where each node represents a credit card transaction. This network may then be analyzed using artificial intelligence and machine learning techniques coupled with visual representations of the interrelated nodes to draw conclusions. An account holder or other system entity may report a fraudulent transaction that employs the holder's account information. A backend system may organize transaction information as a network of data nodes that includes a variety of interrelated information. The backend system may then identify all financial transaction “nodes” within the network that are related or connected by common data. For example, multiple transactions may include a common merchant as the reported fraudulent transaction. The backend may then perform an analysis of the nodes to identify likely fraudulent transactions based on one or more of the data elements for each node.Type: GrantFiled: May 31, 2019Date of Patent: May 3, 2022Assignee: VISA INTERNATIONAL SERVICE ASSOCIATIONInventors: Karthikeyan Kandasamy, Srinivasan Varadharajan, Hemant Deshpande, Prashant Trivedi
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Patent number: 10760814Abstract: A system includes a converter and a controller to control a compressor and operates without receiving power supply from a thermostat. The converter receives a demand signal from the thermostat that is used to power the controller and charge a capacitor. When the thermostat de-asserts the demand signal, the charged capacitor powers the controller, which saves system parameters in a nonvolatile memory and enters a power save mode. The life of the nonvolatile memory is extended by alternately storing the system parameters in different memory locations. The system normalizes outdoor ambient temperature (OAT) during a demand cycle. The system determines OAT slope, which is used to select durations to operate the compressor at different capacities, by performing time based calculations during a demand cycle, demand cycle based calculations at the start of a demand cycle, or time and demand cycle based calculations during a demand cycle.Type: GrantFiled: May 23, 2017Date of Patent: September 1, 2020Assignee: Emerson Climate Technologies, Inc.Inventors: Sahil Popli, Vikram Balasaheb Gholap, Chetan Avinash Sowani, Tanmay Hemant Deshpande, Edward J. Trudeau, Jr.
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Publication number: 20200166237Abstract: A system is provided and includes a first controller, a non-transitory computer-readable medium and a second controller. The first controller is configured to control operation of at least one compressor circuit including one or more compressors. The non-transitory computer-readable medium is configured to store instructions of a stage profiler for execution by the controller. The instructions include: determining a target system capacity profile for the at least one compressor circuit; determining system stage capacities for stages of the at least one compressor circuit; selecting some of the system stage capacities based on the target system capacity profile to provide an available system capacity profile; generating modulation information based on the available system capacity profile and a load request signal; and controlling operation of the one or more compressors based on the modulation information and according to the available system capacity profile.Type: ApplicationFiled: July 12, 2018Publication date: May 28, 2020Applicant: EMERSON CLIMATE TECHNOLOGIES, INC.Inventors: Richard Evans SPEAKER, Chetan Avinash SOWANI, Kamalakkannan MUTHUSUBRAMANIAN, Tanmay Hemant DESHPANDE
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Publication number: 20190370812Abstract: An account holder's portfolio of transactions may be represented as a network of interconnected transaction nodes where each node represents a credit card transaction. This network may then be analyzed using artificial intelligence and machine learning techniques coupled with visual representations of the interrelated nodes to draw conclusions. An account holder or other system entity may report a fraudulent transaction that employs the holder's account information. A backend system may organize transaction information as a network of data nodes that includes a variety of interrelated information. The backend system may then identify all financial transaction “nodes” within the network that are related or connected by common data. For example, multiple transactions may include a common merchant as the reported fraudulent transaction. The backend may then perform an analysis of the nodes to identify likely fraudulent transactions based on one or more of the data elements for each node.Type: ApplicationFiled: May 31, 2019Publication date: December 5, 2019Inventors: Karthikeyan Kandasamy, Srinivasan Varadharajan, Hemant Deshpande, Prashant Trivedi
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Publication number: 20170343230Abstract: A system includes a converter and a controller to control a compressor and operates without receiving power supply from a thermostat. The converter receives a demand signal from the thermostat that is used to power the controller and charge a capacitor. When the thermostat de-asserts the demand signal, the charged capacitor powers the controller, which saves system parameters in a nonvolatile memory and enters a power save mode. The life of the nonvolatile memory is extended by alternately storing the system parameters in different memory locations. The system normalizes outdoor ambient temperature (OAT) during a demand cycle. The system determines OAT slope, which is used to select durations to operate the compressor at different capacities, by performing time based calculations during a demand cycle, demand cycle based calculations at the start of a demand cycle, or time and demand cycle based calculations during a demand cycle.Type: ApplicationFiled: May 23, 2017Publication date: November 30, 2017Applicant: Emerson Climate Technologies, Inc.Inventors: Sahil POPLI, Vikram Balasaheb Gholap, Chetan Avinash Sowani, Tanmay Hemant Deshpande, Edward J. Trudeau, JR.
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Patent number: 9660078Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.Type: GrantFiled: November 25, 2015Date of Patent: May 23, 2017Assignee: Intel CorporationInventors: Cory E. Weber, Mark Y. Liu, Anand Murthy, Hemant Deshpande, Daniel B. Aubertine
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Patent number: 9644515Abstract: An aftertreatment system comprises a liquid exhaust reductant tank. A heat exchanger is positioned downstream of the preheater. The heat exchanger heats the liquid exhaust reductant to a second temperature. The second temperature is sufficient to decompose the liquid exhaust reductant and produce ammonia gas. A storage tank is positioned downstream of the heat exchanger and is structured to store the ammonia gas at a predetermined pressure. The aftertreatment system also includes a selective catalytic reduction system positioned downstream of the storage tank. The aftertreatment system can also include a preheater positioned downstream of the liquid exhaust reductant tank and upstream of the heat exchanger.Type: GrantFiled: March 24, 2015Date of Patent: May 9, 2017Assignee: CUMMINS EMISSION SOLUTIONS, INC.Inventor: Hemant Deshpande
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Publication number: 20160281566Abstract: An aftertreatment system comprises a liquid exhaust reductant tank. A heat exchanger is positioned downstream of the preheater. The heat exchanger heats the liquid exhaust reductant to a second temperature. The second temperature is sufficient to decompose the liquid exhaust reductant and produce ammonia gas. A storage tank is positioned downstream of the heat exchanger and is structured to store the ammonia gas at a predetermined pressure. The aftertreatment system also includes a selective catalytic reduction system positioned downstream of the storage tank. The aftertreatment system can also include a preheater positioned downstream of the liquid exhaust reductant tank and upstream of the heat exchanger.Type: ApplicationFiled: March 24, 2015Publication date: September 29, 2016Applicant: Cummins Emission Solutions, Inc.Inventor: Hemant Deshpande
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Publication number: 20160079423Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.Type: ApplicationFiled: November 25, 2015Publication date: March 17, 2016Applicant: Intel CorporationInventors: Cory E. Weber, Mark Y. Liu, Anand Murthy, Hemant Deshpande, Daniel B. Aubertine
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Patent number: 9231076Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.Type: GrantFiled: December 24, 2014Date of Patent: January 5, 2016Assignee: Intel CorporationInventors: Cory E. Weber, Mark Y. Liu, Anand Murthy, Hemant Deshpande, Daniel B. Aubertine
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Patent number: 9076814Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.Type: GrantFiled: June 6, 2014Date of Patent: July 7, 2015Assignee: Intel CorporationInventors: Cory Weber, Mark Liu, Anand Murthy, Hemant Deshpande, Daniel B. Aubertine
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Publication number: 20150155384Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.Type: ApplicationFiled: December 24, 2014Publication date: June 4, 2015Applicant: Intel CorporationInventors: Cory E. Weber, Mark Y. Liu, Anand Murthy, Hemant Deshpande, Daniel B. Aubertine
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Publication number: 20140284626Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.Type: ApplicationFiled: June 6, 2014Publication date: September 25, 2014Inventors: Cory Weber, Mark Liu, Anand Murthy, Hemant Deshpande, Daniel B. Aubertine
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Patent number: 8779477Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.Type: GrantFiled: August 14, 2008Date of Patent: July 15, 2014Assignee: Intel CorporationInventors: Cory Weber, Mark Liu, Anand Murthy, Hemant Deshpande, Daniel B. Aubertine
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Patent number: 8716806Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a source/drain region in an NMOS portion of a substrate, wherein the source/drain region of the NMOS portion comprises at least one dislocation, and wherein a PMOS source/drain region in a PMOS portion of the substrate does not comprise a dislocation.Type: GrantFiled: April 27, 2012Date of Patent: May 6, 2014Assignee: Intel CorporationInventors: Oleg Golonzka, Hemant Deshpande, Ajay K Sharma, Cory Weber, Ashutosh Ashutosh
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Patent number: 8650491Abstract: Enterprise information handling system storage solutions are configured automatically through a graphical user interface that accepts storage device and storage topology selections from an end user to automatically present a graphical image depicting interconnection devices that interface the storage devices. For example, cables with a color selected by the end user are depicted interfacing storage devices with the selected color. In one embodiment, switches are automatically selected and depicted for the storage devices and storage topology selected by the end user.Type: GrantFiled: December 6, 2007Date of Patent: February 11, 2014Assignee: Dell Products L.P.Inventors: Fenghua Jia, Jason Wallis, Robert Hayes, Sreenivas Sathyanarayana, Hsinlin Lai, Greg Murray, Asmita Phadke, Hemant Deshpande, Jayavel Somasundaram, Kevin Thex
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Publication number: 20120211839Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a source/drain region in an NMOS portion of a substrate, wherein the source/drain region of the NMOS portion comprises at least one dislocation, and wherein a PMOS source/drain region in a PMOS portion of the substrate does not comprise a dislocation.Type: ApplicationFiled: April 27, 2012Publication date: August 23, 2012Inventors: Oleg Golonzka, Hemant Deshpande, Ajay K. Sharma, Cory Weber, Ashutosh Ashutosh
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Patent number: 8193049Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a source/drain region in an NMOS portion of a substrate, wherein the source/drain region of the NMOS portion comprises at least one dislocation, and wherein a PMOS source/drain region in a PMOS portion of the substrate does not comprise a dislocation.Type: GrantFiled: December 17, 2008Date of Patent: June 5, 2012Assignee: Intel CorporationInventors: Oleg Golonzka, Hemant Deshpande, Ajay K. Sharma, Cory Weber, Ashutosh Ashutosh
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Publication number: 20100148270Abstract: Methods and associated structures of forming a microelectronic device are described. Those methods may include forming a source/drain region in an NMOS portion of a substrate, wherein the source/drain region of the NMOS portion comprises at least one dislocation, and wherein a PMOS source/drain region in a PMOS portion of the substrate does not comprise a dislocation.Type: ApplicationFiled: December 17, 2008Publication date: June 17, 2010Inventors: Oleg Golonzka, Hemant Deshpande, Ajay K. Sharma, Cory Weber, Ashutosh Ashutosh