Abstract: A device is provided. The device includes a transistor formed on a semiconductor substrate, the transistor having a conduction channel. The device includes at least one edge dislocation formed adjacent to the conduction channel on the semiconductor substrate. The device also includes at least one free surface introduced above the conduction channel and the at least one edge dislocation.

Abstract: Enterprise information handling system network solutions are automatically validated within each information handling system, between connected information handling systems and to logical groupings within the solution and to the solution as a whole. A validation engine applies validation rules to determine a network solution topology to validate end user information handling system component selections. Invalid information handling system component selections are automatically corrected, disabled or hidden to ensure that end users select valid configurations.

Abstract: Enterprise information handling system storage solutions are configured automatically through a graphical user interface that accepts storage device and storage topology selections from an end user to automatically present a graphical image depicting interconnection devices that interface the storage devices. For example, cables with a color selected by the end user are depicted interfacing storage devices with the selected color. In one embodiment, switches are automatically selected and depicted for the storage devices and storage topology selected by the end user.

Abstract: A MOS device comprises a gate stack comprising a gate electrode disposed on a gate dielectric, a first spacer and a second spacer formed on laterally opposite sides of the gate stack, a source region proximate to the first spacer, a drain region proximate to the second spacer, and a channel region subjacent to the gate stack and disposed between the source region and the drain region. The MOS device of the invention further includes a buried oxide (BOX) region subjacent to the channel region and disposed between the source region and the drain region. The BOX region enables deeper source and drain regions to be formed to reduce transistor resistance and silicide spike defects while preventing gate edge junction parasitic capacitance.

Abstract: A semiconductor device and method for its fabrication are described. An isolation body may be formed prior to formation of an active region. In one embodiment, the isolation body is void-free.