Abstract: A package for multiple integrated circuit dies (e.g., chips). Various common couplers are layered between the chips and package contacts of the package. Each of the chips has a planar surface (e.g., a flat top surface) along which the chips include die contacts. The common couplers lie along the planar surface of each of the chips, and electrically connects the die contacts of the chips to the package contacts of the package. This allows the chips, the common couplers, and the package contacts to be stacked together to form a relatively thin, compact package. The common couplers connect the die contacts of any particular type to the corresponding package contacts of that particular type, such that the die contacts need not have the same layout as the package contacts, thus allowing packages with the same package contact layouts to be used to package chips with varying die contact layouts.

Abstract: A package for an integrated circuit die (e.g., a chip). A routing layer is layered between the chip and package contacts of the package. The chip has a planar surface along which the chip includes die contacts. The routing layer lies along the planar surface of the chip, and electrically connects the die contacts of the chip to the package contacts of the package. This allows the chip, the routing layer, and the package contacts to be stacked together to form a relatively thin, compact package. The routing layer connects the die contacts of the chip to the package contacts of the package, such that the die contacts need not have the same layout as the package contacts, thus allowing packages with the same package contact layouts to be used to package chips with varying die contact layouts. A lead in conductive contact with the package contact.

Abstract: A transistor structure that includes a biased substrate. The transistor structure comprises a barrier semiconductor layer and a channel semiconductor layer immediately beneath the barrier semiconductor layer to form a heterojunction interface with the barrier semiconductor layer, the heterojunction inducing a two-dimensional electron gas (2DEG) within the channel semiconductor layer. A semiconductor substrate is beneath and rigidly coupled to the channel semiconductor layer and the barrier semiconductor layer. A substrate contact layer is disposed immediately beneath the semiconductor substrate. The substrate contact layer is electrically disconnected from the source contact to allow for a different voltage to be applied to the substrate contact layer as compared to the source contact. A biasing circuit is configured to bias the substrate contact layer.

Abstract: A monolithic implementation of an integrated circuit that includes a power transistor and a biasing circuit for biasing the substrate of the power transistor. For example, the integrated circuit comprises a semiconductor substrate; and an epitaxial stack epitaxially grown on the semiconductor substrate. A power transistor uses a portion of the epitaxial stack including a portion of the channel semiconductor layer and a portion of the barrier semiconductor layer. Furthermore, a biasing circuit includes circuit elements that use a respective portion of the epitaxial stack including a respective portion of the channel semiconductor layer and a portion of the barrier semiconductor layer. The biasing circuit is configured to bias a portion of the semiconductor substrate beneath the power transistor.

Abstract: Structures including an optical component and methods of fabricating a structure including an optical component. The structure includes an optical component having a waveguide core, and multiple features positioned adjacent to the waveguide core. The waveguide core contains a first material having a first thermal conductivity, and the features contain a second material having a second thermal conductivity that is greater than the first thermal conductivity.

Abstract: A shield structure for a semiconductor chip comprises a chip mounting region on a base plate and a shell connected to the base plate. The shell is arranged over the base plate to provide a chamber having a volume, and the chip mounting region is arranged within the volume.

Abstract: Structures including an optical component and methods of fabricating a structure including an optical component. The structure includes an optical component having a waveguide core, and multiple features positioned adjacent to the waveguide core. The waveguide core contains a first material having a first thermal conductivity, and the features contain a second material having a second thermal conductivity that is greater than the first thermal conductivity.

Abstract: Structures including an optical component and methods of fabricating a structure including an optical component. The structure includes an optical component having a waveguide core, and multiple features positioned adjacent to the waveguide core. The waveguide core contains a first material having a first thermal conductivity, and the features contain a second material having a second thermal conductivity that is greater than the first thermal conductivity.

Abstract: Structures including an optical component and methods of fabricating a structure including an optical component. The structure includes a substrate, an optical component including a waveguide core, and a back-end-of-line stack including a heat spreader layer. The optical component is positioned in a vertical direction between the substrate and the back-end-of-line stack. The waveguide core contains a first material having a first thermal conductivity, and the heat spreader layer contains a second material having a second thermal conductivity that is greater than the first thermal conductivity of the first material.

Abstract: Structures including an optical component and methods of fabricating a structure including an optical component. The structure includes a waveguide core and a back-end-of-line stack including a first metallization level, a second metallization level, and a heat sink having a metal feature in the second metallization level. The heat sink is positioned adjacent to a section of the waveguide core. The first metallization level including a dielectric layer positioned between the metal feature and the section of the waveguide core.

Abstract: Structures including an optical component and methods of fabricating a structure including an optical component. The structure includes a waveguide core and a back-end-of-line stack including a first metallization level, a second metallization level, and a heat sink having a metal feature in the second metallization level. The heat sink is positioned adjacent to a section of the waveguide core. The first metallization level including a dielectric layer positioned between the metal feature and the section of the waveguide core.

Abstract: Structures including an optical component and methods of fabricating a structure including an optical component. The structure includes an optical component having a waveguide core, and multiple features positioned adjacent to the waveguide core. The waveguide core contains a first material having a first thermal conductivity, and the features contain a second material having a second thermal conductivity that is greater than the first thermal conductivity.

Abstract: Structures including an optical component and methods of fabricating a structure including an optical component. The structure includes a substrate, an optical component including a waveguide core, and a back-end-of-line stack including a heat spreader layer. The optical component is positioned in a vertical direction between the substrate and the back-end-of-line stack. The waveguide core contains a first material having a first thermal conductivity, and the heat spreader layer contains a second material having a second thermal conductivity that is greater than the first thermal conductivity of the first material.

Abstract: An illustrative memory cell disclosed herein includes a bottom electrode, a top electrode positioned above the bottom electrode and an MTJ (Magnetic Tunnel Junction) structure positioned above the bottom electrode and below the top electrode. In this example, the MTJ structure includes a first ferromagnetic material layer positioned above the bottom electrode, a non-magnetic insulation layer positioned above the first ferromagnetic material layer and a second ferromagnetic material layer positioned on the non-magnetic insulation layer, wherein there is a curved, non-planar interface between the non-magnetic insulation layer and the ferromagnetic material layer.

Abstract: One illustrative MRAM cell disclosed herein includes a bottom electrode, a top electrode positioned above the bottom electrode and an MTJ (Magnetic Tunnel Junction) element positioned above the bottom electrode and below the top electrode. In this example, the MTJ element includes a bottom insulation layer positioned above the bottom electrode, a top insulation layer positioned above the bottom electrode; and a first ferromagnetic material layer positioned between the bottom insulation layer and the top insulation layer.

Abstract: Structures for a non-volatile memory element and methods of forming a structure for a non-volatile memory element. The structure includes a non-volatile memory element having a magnetic-tunneling-junction layer stack. The magnetic-tunneling-junction layer stack has a fixed layer that includes a synthetic antiferromagnetic layer. The structure further includes a via positioned adjacent to the magnetic-tunneling-junction layer stack. The via is comprised of a magnetic material.

Abstract: An illustrative memory cell disclosed herein includes a bottom electrode, a top electrode positioned above the bottom electrode and an MTJ (Magnetic Tunnel Junction) structure positioned above the bottom electrode and below the top electrode. In this example, the MTJ structure includes a first ferromagnetic material layer positioned above the bottom electrode, a non-magnetic insulation layer positioned above the first ferromagnetic material layer and a second ferromagnetic material layer positioned on the non-magnetic insulation layer, wherein there is a curved, non-planar interface between the non-magnetic insulation layer and the ferromagnetic material layer.

Abstract: In APT systems and methods, a sample is analyzed by concurrently applying different types of energy to the tip of the sample, thereby causing atom evaporation from the end of the tip. Evaporated atoms are analyzed to determine chemical nature and original position information, which is used to generate a compositional profile. To ensure an accurate profile, the applied energy includes: a D.C. voltage, which lowers the critical energy level (Q) for atom evaporation; first laser pulses, which are applied to opposing first sides of the tip near the end to further lower Q and which are phase-shifted so resulting standing wave patterns of heat distribution have energy maxima that are offset and below a threshold to avoid damage to tip side surfaces; and second laser pulse(s), which is/are applied to second side(s) of the tip near the distal end to reach Q and cause atom evaporation from the end.

Abstract: One illustrative MRAM cell disclosed herein includes a bottom electrode, a top electrode positioned above the bottom electrode and an MTJ (Magnetic Tunnel Junction) element positioned above the bottom electrode and below the top electrode. In this example, the MTJ element includes a bottom insulation layer positioned above the bottom electrode, a top insulation layer positioned above the bottom electrode; and a first ferromagnetic material layer positioned between the bottom insulation layer and the top insulation layer.

Abstract: In APT systems and methods, a sample is analyzed by concurrently applying different types of energy to the tip of the sample, thereby causing atom evaporation from the end of the tip. Evaporated atoms are analyzed to determine chemical nature and original position information, which is used to generate a compositional profile. To ensure an accurate profile, the applied energy includes: a D.C. voltage, which lowers the critical energy level (Q) for atom evaporation; first laser pulses, which are applied to opposing first sides of the tip near the end to further lower Q and which are phase-shifted so resulting standing wave patterns of heat distribution have energy maxima that are offset and below a threshold to avoid damage to tip side surfaces; and second laser pulse(s), which is/are applied to second side(s) of the tip near the distal end to reach Q and cause atom evaporation from the end.