Abstract: A pixel circuit includes a light-emitting device, a first transistor, a second transistor, a first capacitor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor and the fourth transistor are controlled by a light-emitting signal. The third transistor and the fifth transistor are controlled by a scan signal. The light-emitting device, the first transistor, the second transistor, the fourth transistor, and the fifth transistor are serially connected between a system high voltage and a system low voltage. The third transistor is coupled between a data signal and a control terminal of the first transistor. The first capacitor is coupled between a control terminal and a downstream terminal of the second transistor. The fifth transistor is coupled between the downstream terminal of the second transistor and a charging reference voltage. A current of the charging reference voltage is less than a current of the system low voltage.

Abstract: Semiconductor devices using a dielectric structure and methods of manufacturing are described herein. The semiconductor devices are directed towards gate-all-around (GAA) devices that are formed over a substrate and are isolated from one another by the dielectric structure. The dielectric structure is formed over the fin between two GAA devices and cuts a gate electrode that is formed over the fin into two separate gate electrodes. The two GAA devices are also formed with bottom spacers underlying source/drain regions of the GAA devices. The bottom spacers isolate the source/drain regions from the substrate. The dielectric structure is formed with a shallow bottom that is located above the bottoms of the bottom spacers.

Abstract: A pixel circuit includes a storage capacitor, a first switch, and a second switch. The first switch is electrically connected to a first end of the storage capacitor, and configured to provide a data voltage to the first end of the storage capacitor according to a gate signal. The second switch is electrically connected between the first end of the storage capacitor and a second end of the storage capacitor, and configured to receive a first operating voltage from the second end of the storage capacitor and provide the first operating voltage to the first end of the storage capacitor.

Abstract: A wireless docking station is disclosed. The wireless docking station is used for arranging a stylus for signal transmission with an external electronic device. The stylus includes an image capturing module and a first connection port. The wireless docking station includes a placement, a second connection port, a wireless transmission module, a microphone, and a speaker. The placement is used for placing the stylus. The wireless transmission module is connected to the external electronic device, when the image capturing module captures an image, the wireless transmission module transmits the image to the external electronic device. The microphone is used for receiving an external sound signal and transmitting the external sound signal to the external electronic device via the wireless transmission module. The speaker is used for receiving and outputting an output sound signal from the external electronic device via the wireless transmission module.

Abstract: A semiconductor device according to the present disclosure includes first gate-all-around (GAA) devices in a first device area and a second GAA devices in a second device area. Each of the first GAA devices includes a first vertical stack of channel members, a first gate structure over and around the first vertical stack of channel members, and a plurality of inner spacer features. Each of the second GAA devices includes a second vertical stack of channel members and a second gate structure over and around the second vertical stack of channel members. Two adjacent channel members of the first vertical stack of channel members are separated by a portion of the first gate structure and at least one of the plurality of inner spacer features. Two adjacent channel members of the second vertical stack of channel members are separated only by a portion of the second gate structure.

Abstract: Provided is a method of manufacturing a semiconductor device including providing a semiconductor substrate, and forming an epitaxial stack on the semiconductor substrate. The epitaxial stack comprises a plurality of first epitaxial layers interposed by a plurality of second epitaxial layers. The method further includes patterning the epitaxial stack and the semiconductor substrate to form a semiconductor fin, recessing a portion of the semiconductor fin to form source/drain spaces; and laterally removing portions of the plurality of first epitaxial layers exposed by the source/drain spaces to form a plurality of cavities. The method further includes forming inner spacers in the plurality of cavities, performing a treatment process to remove an inner spacer residue in the source/drain spaces, forming S/D features in the source/drain spaces, and forming a gate structure engaging the semiconductor fin.

Abstract: A method for forming a semiconductor device structure is provided. The method includes forming a first gate stack and a second gate stack over a substrate. The substrate has a base, a first fin structure, and a second fin structure over the base, the second fin structure is wider than the first fin structure. The method includes partially removing the first fin structure, which is not covered by the first gate stack, and the second fin structure, which is not covered by the second gate stack. The method includes forming an inner spacer layer over the first fin structure, which is not covered by the first gate stack. The method includes forming a first stressor and a second stressor respectively over the inner spacer layer and the second fin structure, which is not covered by the second gate stack.

Abstract: An apparatus includes an interposer and a plurality of dies stacked on the interposer. The interposer includes a first conductive network of a first trigger bus. Each of the plurality of dies includes a second conductive network of a second trigger bus, and an ESD detection circuit and an ESD power clamp electrically connected between a first power line and a second power line, and electrically connected to the second conductive network of the second trigger bus. The second conductive network of the second trigger bus in each of the plurality of dies is electrically connected to the first conductive network of the first trigger bus. Upon receiving an input signal, the ESD detection circuit is configured to generate an output signal to the corresponding second conductive network of the second trigger bus to control the ESD power clamps in each of the plurality of dies.

Abstract: Some embodiments relate to a semiconductor device on a substrate. An interconnect structure is disposed over the semiconductor substrate. A first conductive pad is disposed over the interconnect structure. A second conductive pad is disposed over the interconnect structure and spaced apart from the first conductive pad. A third conductive pad is disposed over the interconnect structure and spaced apart from the first and second conductive pads. A first ESD protection element is electrically coupled between the first and second conductive pads. A first device under test (DUT) is electrically coupled between the first and third conductive pads.

Abstract: According to one example, a semiconductor device includes a substrate and a fin stack that includes a plurality of nanostructures, a gate device surrounding each of the nanostructures, and inner spacers along the gate device and between the nanostructures. A width of the inner spacers differs between different layers of the fin stack.

Abstract: An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection circuit; a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor; a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor; and a bypass circuit, coupled to the pull-up and pull-down circuits, wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses.

Abstract: A pixel circuit includes a light-emitting device, a first transistor, a second transistor, a first capacitor, a third transistor, a fourth transistor, and a fifth transistor. The first transistor and the fourth transistor are controlled by a light-emitting signal. The third transistor and the fifth transistor are controlled by a scan signal. The light-emitting device, the first transistor, the second transistor, the fourth transistor, and the fifth transistor are serially connected between a system high voltage and a system low voltage. The third transistor is coupled between a data signal and a control terminal of the first transistor. The first capacitor is coupled between a control terminal and a downstream terminal of the second transistor. The fifth transistor is coupled between the downstream terminal of the second transistor and a charging reference voltage. A current of the charging reference voltage is less than a current of the system low voltage.

Abstract: A semiconductor device and a method of forming the same are provided. A semiconductor device according to the present disclosure includes a first source/drain feature, a second source/drain feature, a first semiconductor channel member and a second semiconductor channel member extending between the first and second source/drain features, and a first dielectric feature and a second dielectric feature each including a first dielectric layer and a second dielectric layer different from the first dielectric layer. The first and second dielectric features are sandwiched between the first and second semiconductor channel members.

Abstract: A method of making an electrostatic discharge (ESD) testing structure includes forming, in a first die, a first measurement device. The method further includes forming, in a second die, a fuse, a first trim pad, and a second trim pad. The method further includes forming, between the first die and the second die, a plurality of electrical bonds, wherein a first bond of the plurality of bonds is electrically connected to the first trim pad and a first side of the fuse, and a second bond of the plurality of bonds is electrically connected to the second trim pad and a second side of the fuse.

Abstract: A device includes standard cells in a layout of an integrated circuit, the standard cells includes first and second standard cells sharing a first active region and a second active region. The first standard cell includes first and second gates. The first gate includes a first gate finger and a second gate finger that are arranged over the first active region, for forming the first transistor and the second transistor. The second gate is separate from the first gate, the second gate includes a third gate finger and a fourth gate finger that are arranged over the second active region, for forming the third transistor and the fourth transistor. The second standard cell includes a third gate arranged over the first active region and the second active region, for forming the fifth transistor and the sixth transistor. The first to fourth transistors operate as an electrostatic discharge protection circuit.

Abstract: A device includes first and second standard cells in a layout of an integrated circuit, and first and second active regions. The first standard cell includes an electrostatic discharge (ESD) protection unit, and the second standard cell includes first and second transistors that connect to the ESD protection unit. The first active region includes first, second, and third source/drain regions. The first standard cell includes a first gate arranged across the first active region; and a second gate that is separated from the first gate and is arranged across the first active region and the second active region. The first gate, the first source/drain region and the second source/drain region together correspond to a third transistor of the ESD protection unit. The second gate, the second source/drain region and the third source/drain region together correspond to the first transistor.

Abstract: An electrostatic discharge (ESD) protection circuit is coupled between first and second power supply buses. The ESD protection circuit includes a detection circuit; a pull-up circuit, coupled to the detection circuit, comprising at least a first n-type transistor; a pull-down circuit, coupled to the pull-up circuit, comprising at least a second n-type transistor; and a bypass circuit, coupled to the pull-up and pull-down circuits, wherein the detection circuit is configured to detect whether an ESD event is present on either the first or the second bus so as to cause the pull-up and pull-down circuits to selectively enable the bypass circuit for providing a discharging path between the first and second power supply buses.

Abstract: A mobile charge/discharge device for being electrically connected to a power source and a first power receiving device is disclosed. The mobile charge/discharge device includes a detection circuit detecting a first working power of the power source and a second working power of the first power receiving device; an input port having a first power supply pin for being electrically connected to the power source; a first output port having a second power supply pin for being electrically connected to the first power receiving device; and a controlling circuit controlling the power source to supply the first power receiving device with a power according to one of the first working power and the second working power and supply the mobile charge/discharge device with a power according to the difference of the first working power and the second working power at the same time.

Abstract: The present application discloses am electrical stimulation device for electrically stimulating at least one target zone of an organism. The electrical stimulation device comprises a control unit and an electrical stimulation unit. The electrical stimulation unit includes a frequency synthesizer, an amplifier, a variable resistor, at least one first electrode and at least one second electrode. The frequency synthesizer is coupled to the control unit and generates a frequency signal. The amplifier is coupled to the frequency synthesizer. The variable resistor comprises a resistance and is coupled to the control unit and the amplifier. The first electrode and the second electrode are coupled to the amplifier. The amplifier outputs an electrical stimulation signal according to the frequency signal of the frequency synthesizer and the resistance of the variable resistor to impel the first electrode and the second electrode to generate an electric field.

Abstract: A method of making an electrostatic discharge (ESD) testing structure includes forming, in a first die, a first measurement device. The method further includes forming, in a second die, a fuse, a first trim pad, and a second trim pad. The method further includes forming, between the first die and the second die, a plurality of electrical bonds, wherein a first bond of the plurality of bonds is electrically connected to the first trim pad and a first side of the fuse, and a second bond of the plurality of bonds is electrically connected to the second trim pad and a second side of the fuse.