Patents by Inventor Heng Hsieh

Heng Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for Manufacturing Semiconductor Device with Replacement Gates
    Publication number: 20180337178
    Abstract: A semiconductor device and method includes: forming a first fin and a second fin on a substrate; forming a dummy gate material over the first fin and the second fin; forming a recess in the dummy gate material between the first fin and the second fin; forming a sacrificial oxide on sidewalls of the dummy gate material in the recess; filling an insulation material between the sacrificial oxide on the sidewalls of the dummy gate material in the recess; removing the dummy gate material and the sacrificial oxide; and forming a first replacement gate over the first fin and a second replacement gate over the second fin.
    Type: Application
    Filed: July 31, 2018
    Publication date: November 22, 2018
    Inventors: Chia-Sheng Fan, Bao-Ru Young, Tung-Heng Hsieh
  • MITIGATION OF TIME DEPENDENT DIELECTRIC BREAKDOWN
    Publication number: 20180337053
    Abstract: The present disclosure describes an exemplary replacement gate process that forms spacer layers in a gate stack to mitigate time dependent dielectric breakdown (TDDB) failures. For example, the method can include a partially fabricated gate structure with a first recess. A spacer layer is deposited into the first recess and etched with an anisotropic etchback (EB) process to form a second recess that has a smaller aperture than the first recess. A metal fill layer is deposited into the second recess.
    Type: Application
    Filed: May 18, 2017
    Publication date: November 22, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yi-Jyun HUANG, Bao-Ru YOUNG, Tung-Heng HSIEH
  • Fabricating method for natural cellulose fiber blended with nano silver
    Patent number: 10132009
    Abstract: The present invention provides a fabricating method for natural cellulose fiber blended with nano silver. The fabricating method comprises following steps: Firstly, prepare nano silver colloidal sol by reduction titration for mixture of polyvinyl alcohol (PVA), silver nitrate (AgNO3) and sodium borohydride (NaBH4). Secondly, prepare mixing cellulose serum by blending agitation for mixture of wood pulp, N-methylmorpholine N-oxide (NMMO) and stabilizer. Thirdly, produce spinning dope by blending and dehydrating the nano silver colloidal sol and mixing cellulose serum. Fourthly, produce fibrous tow by Dry-Jet Wet Spinning method in association with coagulation, regeneration in coagulation bath, and water rinse. Finally, obtain final product of natural cellulose fiber blended with nano silver by post treatments of dry, oil and coil in proper order.
    Type: Grant
    Filed: November 9, 2015
    Date of Patent: November 20, 2018
    Assignee: ACELON CHEMICALS AND FIBER CORPORATION
    Inventors: Wen-Tung Chou, Ming-Yi Lai, Kun-Shan Huang, Shao-Hua Chou, Meng-Heng Hsieh
  • Fabricating method for meltblown nonwoven from natural cellulose fiber blended with nano silver
    Patent number: 10132007
    Abstract: The present invention provides a fabricating method for meltblown nonwoven from natural cellulose fiber blended with nano silver, which comprises following steps. Firstly, prepare nano silver colloidal sol by reduction titration for mixture of polyvinyl alcohol (PVA), silver nitrate (AgNO3) and sodium borohydride (NaBH4). Secondly, prepare mixing cellulose serum by blending agitation for mixture of wood pulp, N-methylmorpholine N-oxide (NMMO) and stabilizer. Thirdly, prepare blending mucilage from mixing cellulose serum via blending process. Fourthly, produce spinning dope by blending and dehydrating the nano silver colloidal sol and mixing cellulose serum. Fifthly, produce molten filament tow by meltblown spinning method in association with coagulation, regeneration in coagulation bath, and water rinse.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: November 20, 2018
    Assignee: ACELON CHEMICALS AND FIBER CORPORATION
    Inventors: Wen-Tung Chou, Ming-Yi Lai, Kun-Shan Huang, Shao-Hua Chou, Meng-Heng Hsieh
  • METAL GATE STRUCTURE AND METHODS THEREOF
    Publication number: 20180331199
    Abstract: Provided is a metal gate structure and related methods that include forming a first fin and a second fin on a substrate. In various embodiments, the first fin has a first gate region and the second fin has a second gate region. By way of example, a metal-gate line is formed over the first and second gate regions. In some embodiments, the metal-gate line extends from the first fin to the second fin, and the metal-gate line includes a sacrificial metal portion. In various examples, a line-cut process is performed to separate the metal-gate line into a first metal gate line and a second gate line. In some embodiments, the sacrificial metal portion prevents lateral etching of a dielectric layer during the line-cut process.
    Type: Application
    Filed: July 24, 2018
    Publication date: November 15, 2018
    Inventors: Tzung-Chi LEE, Tung-Heng HSIEH, Bao-Ru YOUNG, Chia-Sheng FAN
  • SEMICONDUCTOR DEVICE AND METHOD
    Publication number: 20180315752
    Abstract: A semiconductor device and method includes: forming a first fin and a second fin on a substrate; forming a dummy gate material over the first fin and the second fin; forming a recess in the dummy gate material between the first fin and the second fin; forming a sacrificial oxide on sidewalls of the dummy gate material in the recess; filling an insulation material between the sacrificial oxide on the sidewalls of the dummy gate material in the recess; removing the dummy gate material and the sacrificial oxide; and forming a first replacement gate over the first fin and a second replacement gate over the second fin.
    Type: Application
    Filed: April 28, 2017
    Publication date: November 1, 2018
    Inventors: Chia-Sheng Fan, Bao-Ru Young, Tung-Heng Hsieh
  • Fabricating method for spunbond nonwoven from natural cellulose fiber blended with nano silver
    Patent number: 10094049
    Abstract: The present invention provides a fabricating method for spunbond nonwoven from natural cellulose fiber blended with nano silver, which comprises following steps. Firstly, prepare nano silver colloidal sol by reduction titration for mixture of polyvinyl alcohol (PVA), silver nitrate (AgNO3) and sodium borohydride (NaBH4). Secondly, prepare mixing cellulose serum by blending agitation for mixture of wood pulp, N-methylmorpholine N-oxide (NMMO) and stabilizer. Thirdly, prepare blending mucilage from mixing cellulose serum via blending process. Fourthly, produce spinning dope by blending and dehydrating the nano silver colloidal sol and mixing cellulose serum. Fifthly, produce molten filament tow by spunbond spinning method in association with coagulation, regeneration, water rinse and high-speed stretching process.
    Type: Grant
    Filed: November 12, 2015
    Date of Patent: October 9, 2018
    Assignee: ACELON CHEMICALS AND FIBER CORPORATION
    Inventors: Wen-Tung Chou, Ming-Yi Lai, Kun-Shan Huang, Shao-Hua Chou, Meng-Heng Hsieh
  • Inflation and deflation pressure regulation system
    Patent number: 10085569
    Abstract: An inflation and deflation pressure regulation system is applicable to an air mattress with at least two air arrays, the inflation and deflation pressure regulation system comprising an inflation and deflation device, a pressure detection unit and a control unit. The inflation and deflation device inflates or deflates the air mattress; the pressure detection unit continuously detects an instantaneous pressure value of the air mattress; the control unit determines whether the instantaneous pressure value detected by the pressure detection unit when the air mattress is in a weight-bearing state has reached a preset pressure value before a preset time has elapsed, and accordingly uses a first inflation and deflation strategy or a second inflation and deflation strategy to control the inflation and deflation device to inflate or deflate the air mattress.
    Type: Grant
    Filed: March 20, 2015
    Date of Patent: October 2, 2018
    Assignee: APEX MEDICAL CORP.
    Inventors: Shih-Chung Liu, Ming-Heng Hsieh
  • Metal gate structure and methods thereof
    Patent number: 10079289
    Abstract: Provided is a metal gate structure and related methods that include forming a first fin and a second fin on a substrate. In various embodiments, the first fin has a first gate region and the second fin has a second gate region. By way of example, a metal-gate line is formed over the first and second gate regions. In some embodiments, the metal-gate line extends from the first fin to the second fin, and the metal-gate line includes a sacrificial metal portion. In various examples, a line-cut process is performed to separate the metal-gate line into a first metal gate line and a second gate line. In some embodiments, the sacrificial metal portion prevents lateral etching of a dielectric layer during the line-cut process.
    Type: Grant
    Filed: July 14, 2017
    Date of Patent: September 18, 2018
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tzung-Chi Lee, Tung-Heng Hsieh, Bao-Ru Young, Chia-Sheng Fan
  • Cell Layout and Structure
    Publication number: 20180253522
    Abstract: A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.
    Type: Application
    Filed: May 4, 2018
    Publication date: September 6, 2018
    Inventors: Tung-Heng Hsieh, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Yu-Cheng Yeh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting
  • METAL GATE STRUCTURE AND METHODS THEREOF
    Publication number: 20180182859
    Abstract: Provided is a metal gate structure and related methods that include forming a first fin and a second fin on a substrate. In various embodiments, the first fin has a first gate region and the second fin has a second gate region. By way of example, a metal-gate line is formed over the first and second gate regions. In some embodiments, the metal-gate line extends from the first fin to the second fin, and the metal-gate line includes a sacrificial metal portion. In various examples, a line-cut process is performed to separate the metal-gate line into a first metal gate line and a second gate line. In some embodiments, the sacrificial metal portion prevents lateral etching of a dielectric layer during the line-cut process.
    Type: Application
    Filed: July 14, 2017
    Publication date: June 28, 2018
    Inventors: Tzung-Chi LEE, Tung-Heng HSIEH, Bao-Ru YOUNG, Chia-Sheng FAN
  • Method and apparatus for integrated circuit layout
    Patent number: 9995998
    Abstract: A method includes receiving a layout of an integrated circuit (IC) device, the layout having an outer boundary and an inner boundary thereby defining a first region between the outer boundary and the inner boundary and placing a first plurality of dummy patterns in the first region, wherein the first plurality of dummy patterns is lithographically printable. The method further includes performing an Optical Proximity Correction (OPC) process, the first plurality of dummy patterns being position within the first region in such a way that prevents sub-resolution assist features from being inserted into the first region by the OPC process.
    Type: Grant
    Filed: June 21, 2016
    Date of Patent: June 12, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Fan Chen, Tung-Heng Hsieh, Chin-Shan Hou, Yu-Bey Wu
  • Semiconductor device, layout of semiconductor device, and method of manufacturing semiconductor device
    Patent number: 9991158
    Abstract: A semiconductor device includes a substrate having an active area, a gate structure over the active area, a lower conductive layer over and electrically coupled to the active area, and an upper conductive layer over and electrically coupled to the lower conductive layer. The lower conductive layer is at least partially co-elevational with the gate structure. The lower conductive layer includes first and second conductive segments spaced from each other. The upper conductive layer includes a third conductive segment overlapping the first and second conductive segments. The third conductive segment is electrically coupled to the first conductive segment, and electrically isolated from the second conductive segment.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: June 5, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tung-Heng Hsieh, Hui-Zhong Zhuang, Chung-Te Lin, Sheng-Hsiung Wang, Ting-Wei Chiang, Li-Chun Tien, Tsung-Chieh Tsai
  • Cell layout and structure
    Patent number: 9984191
    Abstract: A post placement abutment treatment for cell row design is provided. In an embodiment a first cell and a second cell are placed in a first cell row and a third cell and a fourth cell are placed into a second cell row. After placement vias connecting power and ground rails to the underlying structures are analyzed to determine if any can be merged or else removed completely. By merging and removing the closely placed vias, the physical limitations of photolithography may be by-passed, allowing for smaller structures to be formed.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: May 29, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company
    Inventors: Tung-Heng Hsieh, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Yu-Cheng Yeh, Tsung-Chieh Tsai, Juing-Yi Wu, Liang-Yao Lee, Jyh-Kang Ting
  • DUMMY FIN CELL PLACEMENT IN AN INTEGRATED CIRCUIT LAYOUT
    Publication number: 20180137232
    Abstract: In a method of forming an integrated circuit (IC) layout, an empty region in the IC layout is identified by a processor circuit, wherein the empty region is a region of the IC layout not including any active fins. A first portion of the empty region is filled with a first plurality of dummy fin cells, wherein each of the first plurality of dummy fin cells is based on a first standard dummy fin cell, and wherein the first standard dummy fin cell has a first gate width and comprises a first plurality of partitions. A second portion of the empty region is filled with a second plurality of dummy fin cells, wherein each of the second plurality of dummy fin cells is based on a second standard dummy fin cell, and wherein the second standard dummy fin cell has a second gate width and comprises a second plurality of partitions.
    Type: Application
    Filed: December 26, 2017
    Publication date: May 17, 2018
    Inventors: Tung-Heng HSIEH, Tzung-Chi LEE, Yu-Jung CHANG, Bao-Ru YOUNG
  • SYSTEM AND METHOD OF FABRICATING ESD FINFET WITH IMPROVED METAL LANDING IN THE DRAIN
    Publication number: 20180130792
    Abstract: A mandrel is formed over an active region that includes a first region and a second region. The first region and the second region are reserved for the formation of a source and a drain of a FinFET, respectively. A portion of the mandrel formed over the second region is broken up into a first segment and a second segment separated from the first segment by a gap. Spacers are formed on opposite sides of the mandrel. Using the spacers, fins are defined. The fins protrude upwardly out of the active region. A portion of the second region corresponding to the gap has no fins formed thereover. The source is epitaxially grown on the fins in the first region. At least a portion of the drain is epitaxially grown on the portion of the second region having no fins.
    Type: Application
    Filed: January 5, 2018
    Publication date: May 10, 2018
    Inventors: Tzung-Chi Lee, Tung-Heng Hsieh, Bao-Ru Young, Yung Feng Chang
  • Method of forming layout design
    Patent number: 9899263
    Abstract: A method of forming a layout design for fabricating an integrated circuit (IC) is disclosed. The method includes identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design; and generating a set of layout patterns overlapping the identified one or more areas. The plurality of gate structure layout patterns has a predetermined pitch smaller than a spatial resolution of a predetermined lithographic technology. A first layout pattern of the set of layout patterns has a width less than twice the predetermined pitch.
    Type: Grant
    Filed: May 9, 2016
    Date of Patent: February 20, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Tung-Heng Hsieh, Chung-Te Lin, Sheng-Hsiung Wang, Hui-Zhong Zhuang, Min-Hsiung Chiang, Ting-Wei Chiang, Li-Chun Tien
  • Adjustable priority ratios for multiple task queues
    Patent number: 9898341
    Abstract: In some examples, a method includes assigning, to each respective task queue of a plurality of task queues, a respective priority ratio based at least in part on a number of tasks in the respective task queue. The method further includes assigning, by a processor of a plurality of processors, respective tasks from the respective task queues to at least one processor of the plurality of processors in an order based at least in part on the respective priority ratio, wherein the respective priority ratio defines a relative frequency with which tasks from the respective task queue are assigned to the at leak one processor.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: February 20, 2018
    Assignee: Western Digital Technologies, Inc.
    Inventors: Dar-Der Chang, Hsing Heng Hsieh, Charles Dominic Potter
  • System and method of fabricating ESD FinFET with improved metal landing in the drain
    Patent number: 9865589
    Abstract: A mandrel is formed over an active region that includes a first region and a second region. The first region and the second region are reserved for the formation of a source and a drain of a FinFET, respectively. A portion of the mandrel formed over the second region is broken up into a first segment and a second segment separated from the first segment by a gap. Spacers are formed on opposite sides of the mandrel. Using the spacers, fins are defined. The fins protrude upwardly out of the active region. A portion of the second region corresponding to the gap has no fins formed thereover. The source is epitaxially grown on the fins in the first region. At least a portion of the drain is epitaxially grown on the portion of the second region having no fins.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: January 9, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Tzung-Chi Lee, Tung-Heng Hsieh, Bao-Ru Young, Yung Feng Chang
  • DUMMY FIN CELL PLACEMENT IN AN INTEGRATED CIRCUIT LAYOUT
    Publication number: 20180004882
    Abstract: In a method of forming an integrated circuit (IC) layout, an empty region in the IC layout is identified by a processor circuit, wherein the empty region is a region of the IC layout not including any active fins. A first portion of the empty region is filled with a first plurality of dummy fin cells, wherein each of the first plurality of dummy fin cells is based on a first standard dummy fin cell, and wherein the first standard dummy fin cell has a first gate width and comprises a first plurality of partitions. A second portion of the empty region is filled with a second plurality of dummy fin cells, wherein each of the second plurality of dummy fin cells is based on a second standard dummy fin cell, and wherein the second standard dummy fin cell has a second gate width and comprises a second plurality of partitions.
    Type: Application
    Filed: June 29, 2016
    Publication date: January 4, 2018
    Inventors: Tung-Heng HSIEH, Bao-Ru YOUNG, Yu-Jung CHANG, Tzung-Chi LEE