Abstract: One aspect is a method of manufacturing a semiconductor device and semiconductor device. One embodiment provides a plurality of modules. Each of the modules includes a carrier and at least one semiconductor chip attached to the carrier. A dielectric layer is applied to the modules to form a workpiece. The dielectric layer is structured to open at least one of the semiconductor chips. The workpiece is singulated to obtain a plurality of devices.

Abstract: A method and a system for a reliable LED semiconductor device are provided. In one embodiment, the device comprises a carrier, a light emitting diode disposed on the carrier, an encapsulating material disposed over the light emitting diode and the carrier, at least one through connection formed in the encapsulating material, and a metallization layer disposed and structured over the at least one through connection.

Abstract: A laminate electronic device comprises a first semiconductor chip, the first semiconductor chip defining a first main face and a second main face opposite to the first main face, and having at least one electrode pad on the first main face. The laminate electronic device further comprises a carrier having a first structured metal layer arranged at a first main surface of the carrier. The first structured metal layer is bonded to the electrode pad via a first bond layer of a conductive material, wherein the first bond layer has a thickness of less than 10 ?m. A first insulating layer overlies the first main surface of the carrier and the first semiconductor chip.

Abstract: A component has a device applied to a device carrier, a first conducting layer grown onto the device and onto the device carrier, and an insulating material applied to the first conducting layer such that only a portion of the first conducting layer is covered.

Abstract: A method for producing a power semiconductor module having surface mountable flat external contact areas is disclosed. At least one power semiconductor chip is fixed by its rear side on a drain external contact. An insulation layer covers the top side over the side edges of the semiconductor chip as far as the inner housing plane was a leaving free the source and gate contact areas on the top side of the semiconductor chip and also was partly leaving free the top sides of the corresponding external contacts.

Abstract: A method of manufacturing a laminate electronic device is disclosed. One embodiment provides a carrier, the carrier defining a first main surface and a second main surface opposite to the first main surface. The carrier has a recess pattern formed in the first main surface. A first semiconductor chip is attached on one of the first and second main surface. A first insulating layer overlying the main surface of the carrier on which the first semiconductor chip is attached and the first semiconductor chip is formed. The carrier is then separated into a plurality of parts along the recess pattern.

Abstract: A laminate electronic device comprises a first semiconductor chip, the first semiconductor chip defining a first main face and a second main face opposite to the first main face, and having at least one electrode pad on the first main face. The laminate electronic device further comprises a carrier having a first structured metal layer arranged at a first main surface of the carrier. The first structured metal layer is bonded to the electrode pad via a first bond layer of a conductive material, wherein the first bond layer has a thickness of less than 10 ?m. A first insulating layer overlies the first main surface of the carrier and the first semiconductor chip.

Abstract: A semiconductor device and method is disclosed. One embodiment provides a substrate and a first semiconductor chip applied over the substrate. A first electrically conductive layer is applied over the substrate and the first semiconductor chip. A first electrically insulating layer is applied over the first electrically conductive layer. A second electrically conductive layer is applied over the first electrically insulating layer.

Abstract: A power semiconductor device has a semiconductor chip stack and lines within a housing. The lines electrically connect large-area contact regions of power semiconductor device components within the housing to one another. In this case, at least one of the lines has a large-area planar conductive layer. This planar conductive area electrically connects the large-area contact regions to one another.

Abstract: This application relates to a method of manufacturing an electronic device comprising placing a first chip on a carrier; applying an insulating layer over the first chip and the carrier; applying a metal ions containing solution to the insulating layer for producing a first metal layer of a first thickness; and producing a second metal layer of a second thickness on the insulating layer wherein at least one of the first metal layer and the second metal layer comprises at least a portion that is laterally spaced apart from the respective other metal layer.

Abstract: One aspect is a method of manufacturing a semiconductor device and semiconductor device. One embodiment provides a plurality of modules. Each of the modules includes a carrier and at least one semiconductor chip attached to the carrier. A dielectric layer is applied to the modules to form a workpiece. The dielectric layer is structured to open at least one of the semiconductor chips. The workpiece is singulated to obtain a plurality of devices.

Abstract: Data carrier for contactless data transmission comprising a substrate, a chip having at least one connection pad, wherein the chip is arranged by its side remote from the connection pad on the substrate and a first copper-coated prepreg layer 40 is arranged on the chip and at least partly on the substrate and has a contact opening to the connection pad. A plated-through hole is situated within the contact opening for producing an electrically conductive connection between the connection pad of the chip 30 and the copper layer of the first copper-coated prepreg layer, wherein a first antenna structure 48 is formed in the copper layer of the first copper-coated prepreg layer.

Abstract: An integrated circuit device includes a semiconductor device having an integrated circuit. A gas-phase deposited insulation layer is disposed on the semiconductor device, and a conducting line is disposed over the gas-phase deposited insulation layer.

Abstract: One aspect is a method including providing a carrier having a first conducting layer, a first insulating layer over the first conducting layer, and at least one through-connection from a first face of the first insulating layer to a second face of the first insulating layer; attaching at least two semiconductor chips to the carrier; applying a second insulating layer over the carrier; opening the second insulating layer until the carrier is exposed; depositing a metal layer over the opened second insulating layer; and separating the at least two semiconductor chips after depositing the metal layer.

Abstract: This application relates to a method of manufacturing an electronic device comprising placing a first chip on a carrier; applying an insulating layer over the first chip and the carrier; applying a metal ions containing solution to the insulating layer for producing a first metal layer of a first thickness; and producing a second metal layer of a second thickness on the insulating layer wherein at least one of the first metal layer and the second metal layer comprises at least a portion that is laterally spaced apart from the respective other metal layer.

Abstract: A method for producing a dielectric layer extending between two or more elements of an electronic component includes arranging a free-standing dielectric layer above the elements and a deformable support layer below the elements. The free-standing dielectric layer is laminated onto at least a portion of the first surface of the first element and onto at least a portion of the first surface of the second element such that a portion of the dielectric layer extends between the first surface of the first element and the first surface of the second element.

Abstract: A method for producing a power semiconductor module having surface mountable flat external contact areas is disclosed. At least one power semiconductor chip is fixed by its rear side on a drain external contact. An insulation layer covers the top side over the side edges of the semiconductor chip as far as the inner housing plane was a leaving free the source and gate contact areas on the top side of the semiconductor chip and also was partly leaving free the top sides of the corresponding external contacts.

Abstract: An integrated circuit device includes a semiconductor device having an integrated circuit. A gas-phase deposited insulation layer is disposed on the semiconductor device, and a conducting line is disposed over the gas-phase deposited insulation layer.

Abstract: A semiconductor device and method is disclosed. One embodiment provides a substrate and a first semiconductor chip applied over the substrate. A first electrically conductive layer is applied over the substrate and the first semiconductor chip. A first electrically insulating layer is applied over the first electrically conductive layer. A second electrically conductive layer is applied over the first electrically insulating layer.

Abstract: A semiconductor device is disclosed. One embodiment includes a carrier, a semiconductor chip attached to the carrier, a first conducting line having a first thickness and being deposited over the semiconductor chip and the carrier and a second conducting line having a second thickness and being deposited over the semiconductor chip and the carrier. The first thickness is smaller than the second thickness.