Abstract: A power semiconductor module having surface-mountable flat external contact areas and a method for producing the same is disclosed. In one embodiment, the top sides of the external contacts form an inner housing plane, on which at least one power semiconductor chip is fixed by its rear side on a drain external contact. An insulation layer covers the top side over the edge sides of the semiconductor chip as far as the inner housing plane whilst leaving free the source and gate contact areas on the top side of the semiconductor chip and also whilst partly leaving free the top sides of the corresponding external contacts. Arranged on the insulation layer is a connecting conductive layer between the source contact areas on the top side of the semiconductor chip and the top sides of the source external contacts, and also a gate connecting layer from the gate contact areas to the top side of the gate external contact.

Abstract: A component has a device applied to a device carrier, a first conducting layer grown onto the device and onto the device carrier, and an insulating material applied to the first conducting layer such that only a portion of the first conducting layer is covered.

Abstract: A method for producing a dielectric layer extending between two or more elements of an electronic component includes arranging a free-standing dielectric layer above the elements and a deformable support layer below the elements. The free-standing dielectric layer is laminated onto at least a portion of the first surface of the first element and onto at least a portion of the first surface of the second element such that a portion of the dielectric layer extends between the first surface of the first element and the first surface of the second element.

Abstract: Power semiconductor module comprising surface-mountable flat external contact areas and method for producing the same The invention relates to a power semiconductor module (1) comprising surface-mountable flat external contact areas (3) and a method for producing the same. The top sides (10) of the external contacts (3) form an inner housing plane (11), on which at least one power semiconductor chip (6) is fixed by its rear side (8) on a drain external contact (13). An insulation layer (14) covers the top side (7) over the edge sides (15 to 18) of the semiconductor chip (6) as far as the inner housing plane (11) whilst leaving free the source and gate contact areas on the top side (7) of the semiconductor chip (6) and also whilst partly leaving free the top sides (10) of the corresponding external contacts (19 and 20).

Abstract: A power semiconductor device (1) has a semiconductor chip stack (4) and lines (5) within a housing (6). The lines electrically connect large-area contact regions (7) of power semiconductor device components (8) within the housing (6) to one another. In this case, at least one of the lines (5) has a large-area planar conductive layer (9). This planar conductive area (9) electrically connects the large-area contact regions (7) to one another.