Abstract: A quadrature oscillator according to the embodiments herein comprising two pairs of main transistors, two pairs of resonators and two pairs of injection transistors. The quadrature oscillator is split into two halves, which are separated in the chip layout. That is the two pairs of resonators are separated from each other, and the two pairs of the main transistors are separated from the resonator they coupled to such that the quadrature oscillator is separated into two spaced apart oscillator halves connected by transmission lines.

Abstract: An analog PLL employs digital circuitry for calibration and characterization, precisely setting and maintaining the bandwidth of the PLL. A digital calibration circuit calibrates the value of a resistor or capacitor in the loop filter to yield a desired RC product. A digital control circuit reads time-to-digital converters (TDC) digitizing the length of the CU and CD pulses from the phase-frequency detector (PFD) to the charge pump (CP) during a frequency change. These pulse lengths are summed to yield a measured integral CP current. The control circuit determines an integral CP current that yields a desired bandwidth, regardless of the VCO tuning sensitivity, based on the calibrated RC product. The CP current is then adjusted by the ratio of determined integral CP current to the measured integral CP current. The digital circuits do not increase power consumption or adversely affect system operation.

Abstract: A method of establishing connection between a first node in a wireless network and a second node in said wireless network, wherein each of said first and second nodes comprise a primary radio receiver and a wake up receiver, each of said nodes comprising a Radio Frequency, RF, switch, arranged to connect one of said primary or secondary radios to a radio antenna, said method comprising the steps of transmitting, by said first node, to a wake-up receiver of a second radio node, a wake-up signal that indicates a frequency channel on which the second radio node is to transmit a response, receiving, by said first node, in response to transmitting said wake-up signal, response from said second radio node on the frequency channel indicated, and establishing, by said first node, a connection between said first and second nodes in order to transfer data between said first and second nodes. The present disclosure also relates to corresponding mesh nodes and a computer program product.

Abstract: A position of a mobile communication device is determined. This involves the mobile communication device performing reception, from a network node that serves the mobile communication device, a request for sensing of a local area in accordance with one or more parameters that guide how and/or where the sensing is to be performed. In response to the request for the sensing of the local area, sense data is produced by performing the sensing in accordance with the one or more parameters. The sense data is communicated to the network node. In response to communicating the sense data to the network node, a position of the mobile communication device is received.

Abstract: A beamforming apparatus (10) performs beamforming via a plurality of antenna elements (12) by using per-branch sign reversal circuits (16) that approximate the per-branch phase values associated with a particular beam direction or shape by selectively reversing or not reversing the polarities of the individual branch signals (18). Eliminating continuous-valued or high-resolution phasing control from the branch circuits (14) that are fed into or from the respective antenna elements (12) simplifies the branch circuitry, thereby reducing the physical space needed for the branch circuits (14) and reducing loss and noise within the branch circuits (14). Further, operating the plurality of antenna elements (12) as two or more groups (24) and controlling the differential phase between the groups (24) advantageously reduces the errors arising from the approximation of the per-branch phase values.

Abstract: The present disclosure presents a front-end assembly (100) for an antenna array. The front-end assembly (100) comprises at least four front-end circuits (200), each operatively connectable to one single antenna element (35) of the antenna array (30) and interconnected to form a matrix structure comprising at least two column signal lines (110) and at least two row signal lines (120). Each front-end circuit (200) comprises a first mixer circuit (210) and a second mixer circuit (220). Said interconnection is formed by at least two first mixer circuits (210) being operatively connected to each other in parallel in each column signal line (110) and at least two second mixer circuits (220) being operatively connected to each other in parallel in each row signal line (120). Further to this, an antenna front-end assembly (10), an integrated circuit, a network node, a wireless device and a method for controlling the front end assembly (100) are presented.

Abstract: A position of a mobile communication device is determined by obtaining a first set of candidate signal templates, wherein each candidate signal template in the first set of candidate signal templates corresponds to a respective candidate position of a first set of candidate positions, and wherein magnitude values in each candidate signal template in the first set of candidate signal templates are encoded in accordance with a first magnitude encoding strategy. A first radar echo signal is obtained, and a first test signal is produced by encoding magnitude values of the first radar echo signal in accordance with the first magnitude encoding strategy. The first test signal is correlated with each candidate signal template in the first set of candidate signal templates to obtain a first set of respective correlation results.

Abstract: A transmitter circuit has a signal input for receiving an analog input signal and a local oscillator (LO) input for receiving an LO signal. A mixer circuit has a first input, a second input, and an output. The second input of the mixer circuit is connected to a signal input of the transmitter circuit. A PA circuit has an input connected to the output of the mixer circuit, and an output. A control circuit generates a phase-control signal and a gain-control signal in response to an envelope of the analog input signal. A phase-control circuit generates a phase-adjusted LO signal in response to the LO signal and the phase-control signal and supplies the phase-adjusted LO signal to the first input of the mixer circuit. A gain-control circuit controls a gain of the transmitter circuit in response to the gain-control signal.

Abstract: An integrated, distributed, multiple Phase Locked Loop (multi-PLL) system locks the frequency and phase of multiple secondary PLLs to that of a primary PLL. The VCOs in all PLLs receive both first and second control signals. The primary PLL's primary VCO control signal is generated conventionally. using a reference periodic signal input, and is output to all secondary PLLs: hence the secondary PLLs operate at the primary PLL frequency. The primary PLL also outputs its divided periodic signal. Each secondary PLL compares its local divided periodic signal to the one received from the primary PLL (rather than to a reference signal input) in its phase locking loop. generating a secondary VCO input that locks the secondary PLL circuit phase to that of the primary PLL circuit. Selected secondary PLLs can be set to a phase offset from the primary PLL, such as by controlled DC current injected into the charge pump output.

Abstract: A multi-carrier transceiver receives and transmits wireless communication signals on multiple carriers simultaneously. To generate Local Oscillator (LO) signals for mixers operating at different frequencies, a multi-frequency LO signal generating circuit includes a set of integer-N Phase Locked Loop (PLL) circuits. All PLL circuits receive the same reference frequency, but output different frequency LO signals, each at an integer multiple of the reference frequency. The LO signal frequencies are thus on an equidistant frequency grid having a granularity of the reference frequency. Spurs are also at multiples of the reference frequency, and can be easily filtered. A fractional-N PLL circuit may generate the reference frequency, making the frequency grid adjustable.

Abstract: A bias circuit for a PA. A first transistor has its drain terminal and its gate terminal connected to a first circuit node and its source terminal connected to a first supply terminal, a first current source connected to the first circuit node, and a first resistor connected between the first and second circuit nodes. A second transistor receives a first component of a differential input signal to the PA at its gate terminal, has its drain terminal connected to the second circuit node and its source terminal connected to a second supply terminal, and a third transistor receives a second component of the differential input signal to the PA at its gate terminal, having its drain terminal connected to the second circuit node and its source terminal connected to a second supply terminal. The gates terminals of the second and third transistors are biased by a first voltage.

Abstract: A frequency determination device for determining a frequency relationship between a reference signal and a clock signal. Each constituent TDC is configured to provide a digitally represented constituent output signal in response to receiving a constituent reference signal and a constituent clock signal, and the frequency determination device is configured to successively provide respectively delayed versions of the constituent clock signal of a first constituent TDC as respective constituent clock signals to the other constituent TDC:s. The reference signal provider is configured to provide the respective constituent reference. The switching circuitry is configured to provide the reference signal as the constituent clock signal to the first constituent TDC. The determination circuitry is configured to determine a number of consecutively same-valued symbols in a concatenation of the digitally represented constituent output signals of the constituent TDC:s, and to determine the frequency relationship.

Abstract: A Time to Digital Converter (TDC) arrangement includes a first delay circuit configured to receive a signal with N phases; a set of phase detectors configured to compare each phase of the signal with a reference signal; a logic circuit configured to receive output signals from the set of phase detectors and detect which phase signal that is the closest signal leading or lagging the reference signal; a first multiplexer configured to receive outputs from the first delay circuit and the logic circuit; a second delay circuit configured to delay the reference signal; a TDC configured to receive output signals from the first multiplexer and the second delay circuit; an adder configured to sum outputs from the logic circuit and the TDC and generate an output signal of the TDC arrangement.

Abstract: A time-to-digital converter (TDC) circuitry for converting a phase difference between an input reference signal and an input clock signal to a digitally represented output signal. The TDC circuitry comprises multiple constituent TDCs, a reference signal provider, and a digital signal combiner. Each TDC is configured to convert a phase difference between a constituent reference signal and a constituent clock signal to a digitally represented constituent output signal. The reference signal provider is configured to provide the respective constituent reference signals to each of the TDCs. In at least a parallel operation mode of the TDC circuitry, each respective constituent reference signal comprises a respectively delayed version of the input reference signal with different respective delays for at least two of the respective constituent reference signals.

Abstract: A bias circuit for a PA. A first transistor has its drain terminal and its gate terminal connected to a first circuit node and its source terminal connected to a first supply terminal, a first current source connected to the first circuit node, and a first resistor connected between the first and second circuit nodes. A second transistor receives a first component of a differential input signal to the PA at its gate terminal, has its drain terminal connected to the second circuit node and its source terminal connected to a second supply terminal, and a third transistor receives a second component of the differential input signal to the PA at its gate terminal, having its drain terminal connected to the second circuit node and its source terminal connected to a second supply terminal. The gates terminals of the second and the third transistors are biased by a first voltage.

Abstract: A method of signal block reception with automatic gain control (AGC) for a receiver is disclosed. The receiver is configured for at least a sleep mode and an active mode. The signal blocks are non-adjacent in time, and each signal block is configured to be received in entirety using a valid AGC setting determined based on a previous signal block. The method comprises, when switching from the sleep mode to the active mode for continuous reception of a signal block, receiving a first set of samples of the signal block, determining an applicable AGC setting based on the first set of samples of the signal block, and receiving a second set of samples of the signal block using the applicable AGC setting determined based on the first set of samples. Corresponding apparatus, receiver, wireless communication device and computer program product are also disclosed.

Abstract: A radar sensing function is performed in a mobile communication device that operates in a Time Division Duplex (TDD) wireless communication system having an air interface that comprises a plurality of uplink symbol times, a plurality of downlink symbol times, a plurality of TDD transmission direction transition periods, and a plurality of transition pairs of symbol times, wherein each of the transition pairs of symbol times comprises one of the uplink symbol times and one of the downlink symbol times, and each of the TDD transmission direction transition periods is associated with one of the plurality of transition pairs of symbol times and is immediately preceded by a first one of the uplink and downlink symbol times of the associated transition pair of symbol times and is immediately followed by a second one of the uplink and downlink symbol times of the associated transition pair of symbol times.

Abstract: A radar sensing function is performed in a mobile communication device that operates in a Time Division Duplex (TDD) wireless communication system having an air interface that comprises a plurality of uplink symbol times associated with symbols transmitted in an uplink direction and a plurality of downlink symbol times associated with symbols transmitted in a downlink direction, and in which each transmitted symbol from a plurality of transmitted symbols has a corresponding cyclic prefix that is transmitted immediately before the corresponding transmitted symbol, and that is a repetition of an end part of the corresponding transmitted symbol. Information about a path delay between the mobile communication device and a receiver is used as one of one or more bases to determine a timing of a radar operation window having a duration that is shorter than a duration of a cyclic reception window of the receiver and comprising a radar signal transmission time and a radar backscatter reception period.

Abstract: A wireless device features a low-power, limited-functionality, narrowband, homodyne wakeup receiver with a free running local oscillator. This enables a very attractive combination of low power consumption and high selectivity. The network supports these receivers by adopting a wakeup message structure that supports oscillator frequency calibration, and that tolerates loss of parts of the signal spectrum. Wakeup signals are transmitted frequently to allow the wakeup receivers (whether targeted by a wakeup signal or not) to calibrate their LO frequencies. The frequencies of the wakeup signals can be constant, or follow a hopping pattern for increased immunity to interference. The wakeup signals can use multiple carriers to increase robustness to loss of parts of the signal spectrum, particularly near the LO frequency in a homodyne receiver. The carriers use amplitude modulation (OOK), with either different or equal sequences.

Abstract: A transmitter and method therein for transmitting a signal to a receiver in a wireless communication system are disclosed. The transmitter is configured to modulate a signal using two different modulations, a combination of binary amplitude shift keying, ASK, and binary frequency shift keying, FSK, and transmit the modulated signal.