Abstract: A system for phase control of a Phased Locked Loop, PLL, is disclosed. The system includes the PLL. The PLL includes an oscillator configured to generate an output signal; a frequency divider configured to generate a feedback signal by dividing the output signal from the oscillator; a first phase detector arrangement configured to output a first control signal to control the oscillator in response to a detection of a phase deviation between a reference signal and the feedback signal. A second phase detector is configured to receive the feedback signal from the frequency divider and the reference signal, and generate an output signal. A phase calibration circuit is configured to receive the output signal from the second phase detector and generate a second control signal to adjust a phase of the output signal of the oscillator.

Abstract: A phase locked loop, for a particularly in a beamforming system comprises a digital loop filter to provide a digital control word to a controllable oscillator; a frequency divider configured to provide a first feedback signal and a second feedback signal in response to an oscillator signal, the second feedback signal delayed with respect to the first feedback signal; a first comparator path configured to receive the first feedback signal and a second comparator path configured to receive the second feedback signal, each of the first and second comparator path configured to provide a respective phase delay signal to the digital loop filter in response to a respective adjustment signal and a phase deviation between a common reference signal and the respective feedback signal.

Abstract: A phase locked loop, for a particularly in a beamforming system comprises a loop filter (1) to provide a control signal (FC) to a controllable oscillator (2); a frequency divider (3) configured to provide a first feedback signal (FB) and a second feedback signal (FBD) in response to an oscillator signal (FO), wherein the second feedback signal (FBD) is delayed with respect to the first feedback signal (FB). An interpolator is configured to receive the first and the second feedback signal (FB) and to provide an interpolated signal thereof between the first and second feedback signal and in response to a phase control word. A comparator path is configured to receive the interpolated signal and to provide a respective signal to the loop filter (1) in response to a phase deviation between a common reference signal (FR) and the interpolated signal.

Abstract: A phase locked loop, for a particularly in a beamforming system comprises a loop filter (1) to provide a control signal (FC) to a controllable oscillator (2); a frequency divider (3) configured to provide a first feedback signal (FB) and a second feedback signal (FBD) in response to an oscillator signal (FO), the second feedback signal (FBD) delayed with respect to the first feedback signal (FB); a first comparator path (4) configured to receive the first feedback signal (FB) and a second comparator path (5) configured to receive the second feedback signal (FBD), each of the first and second comparator path (4, 5) configured to provide a respective current signal (CS1, CS2) to the loop filter (1) in response to a respective adjustment signal (FA1, FA2) and a phase deviation between a common reference signal (FR) and the respective feedback signal (FB, FBD).

Abstract: A transceiver suitable for frequency division duplex (FDD) communication is disclosed. In one exemplary embodiment, a transmitter leakage reduction circuit for a transceiver is described. The transmitter leakage reduction circuit comprises an auxiliary power amplifier, first and second filters, and a signal transmission arrangement. The auxiliary power amplifier is configured to provide an auxiliary power amplifier output signal that represents an output signal of a power amplifier of the transmitter with a controllable phase shift or gain output. The first and second filters are configured to attenuate any signals in the receive frequency band of the respective power amplifier output signal and auxiliary power amplifier output signal. The signal transmission arrangement is configured to suppress a contribution of the power amplifier output signal from a signal received from an RF connecting point using the auxiliary power amplifier output signal to obtain a received signal that is input to the receiver.

Abstract: A differential amplifier comprises a first differential circuitry structure including a first part comprising at least one branch of transistors and a second part comprising at least one branch of transistors, and a second circuitry structure. The second circuitry structure has a first non-linear device and a second non-linear device. The non-linear devices each comprise a transistor having a control node connected to a differential output terminals of the differential amplifier. A common center node of the non-linear devices is connected to a control node of one of the transistors of each branch of the first part having a differential output terminal. Amplifier applications, communication devices and network nodes are also disclosed.

Abstract: Exemplary embodiments include an electronic frequency-divider circuit comprising a multi-phase generator circuit configured to: receive an oscillating input signal having a frequency f; determine an integer divide ratio Q based on a first control signal input; and based on the oscillating input signal, generate an N-phase output signal having a frequency f-divided-by-M, wherein M is an integer and adjacent phases of the N-phase output signal are separated by 360-divided-by-(M-times-Q) degrees. The divider circuit can also include a control circuit configured to receive a control input and, based on the control input: provide the first control signal to the multi-phase generator circuit; and select a particular phase of the N-phase output signal. Exemplary embodiments also include a phase-locked loop circuits, transceiver circuits, radio stations, and methods of frequency-dividing an oscillating signal.

Abstract: A phase locked loop, for a particularly in a beamforming system comprises a digital loop filter to provide a digital control word to a controllable oscillator; a frequency divider configured to provide a first feedback signal and a second feedback signal in response to an oscillator signal, the second feedback signal delayed with respect to the first feedback signal; a first comparator path configured to receive the first feedback signal and a second comparator path configured to receive the second feedback signal, each of the first and second comparator path configured to provide a respective phase delay signal to the digital loop filter in response to a respective adjustment signal and a phase deviation between a common reference signal and the respective feedback signal.

Abstract: A digital solution for phase control of an output of a phase-locked loop (PLL) (100) is provided to achieve a desired phase shift at the output of the PLL (100). To that end, a fraction of the pulses of a PLL feedback signal are time shifted to achieve a desired average time shift associated with the desired phase shift. As a result, a desired phase shift is generated at the output of the PLL (100), while a desired devisor of the feedback signal is maintained on average. The resulting digital solution provides highly accurate phase control.

Abstract: Exemplary embodiments include an electronic frequency-divider circuit comprising a multi-phase generator circuit configured to: receive an oscillating input signal having a frequency f; determine an integer divide ratio Q based on a first control signal input; and based on the oscillating input signal, generate an N-phase output signal having a frequency f-divided-by-M, wherein M is an integer and adjacent phases of the N-phase output signal are separated by 360-divided-by-(M-times-Q) degrees. The divider circuit can also include a control circuit configured to receive a control input and, based on the control input: provide the first control signal to the multi-phase generator circuit; and select a particular phase of the N-phase output signal. Exemplary embodiments also include a phase-locked loop circuits, transceiver circuits, radio stations, and methods of frequency-dividing an oscillating signal.

Abstract: An integrated circuit comprises a first amplifier circuit with a push-pull amplifier configured to be calibrated to a low second order distortion. The integrated circuit further comprises a second amplifier circuit with at least one push-pull amplifier, wherein a size ratio between sizes of the transistors is adjustable by adjusting the size of at least one transistor device. The size ratio can be consecutively adjusted to a plurality of values, and for each value, a first output signal of a push-pull amplifier with an applied test signal and a second output signal of a push-pull amplifier without applied test signal, are determined. The size ratio for which a difference between the push-pull amplifier output signals is closest to zero is determined, and the push-pull amplifier of the first amplifier circuit is calibrated in dependence of the determined size ratio.

Abstract: An electronic circuit arranged to receive an oscillating signal and output an output signal at a frequency having a frequency relation with the oscillating signal defined by a divide ratio is provided.

Abstract: A quadrature phase detector circuit for a multi-antenna radio circuit comprising a plurality of frequency synthesizers using a common reference oscillator signal is disclosed.

Abstract: A transceiver front-end for a communication device is connectable to a signal transmission and reception arrangement adapted to transmit a transmit signal having a transmit frequency and to receive a receive signal having a receive frequency. The transceiver front-end is also connectable to a transmitter adapted to produce the transmit signal, and to a receiver adapted to process the receive signal. The transceiver front-end comprises a transmit frequency suppression filter arrangement and a receive frequency suppression filter arrangement. The transmit frequency suppression filter arrangement is adapted to suppress transfer of a signal having the transmit frequency and to pass a signal having the receive frequency. The receive frequency suppression filter arrangement is adapted to suppress transfer of a signal having the receive frequency and to pass a signal having the transmit frequency.

Abstract: An electronic circuit (51) configured to provide an adjustable impedance at a first frequency comprises a transconductance amplifier (52) arranged to provide a current signal proportional to an input signal at an input terminal; at least one conversion arrangement, each comprising a mixer arrangement (53) utilizing a first local oscillator signal at said frequency to down-convert the current signal to a baseband voltage signal; a filtering arrangement (54, 55) connected to said mixer arrangement (53) and comprising at least a resistor and a capacitor in parallel; and a mixer arrangement (56) utilizing a second local oscillator signal at said frequency to up-convert a voltage signal present at the filter arrangement to an up-converted voltage signal; and a transconductance amplifier (57) arranged to provide a second current signal proportional to the up-converted voltage signal and to feed back said second current signal to the input terminal of the electronic circuit.

Abstract: A differential amplifier comprises a first differential circuitry structure including a first part comprising at least one branch of transistors and a second part comprising at least one branch of transistors, and a second circuitry structure. The second cicuitry structure has a first non-linear device and a second non-linear device. The non-linear devices each comprise a transistor having a control node connected to a differential output terminals of the differential amplifier. A common centre node of the non-linear devices is connected to a control node of one of the transistors of each branch of the first part having a differential output terminal. Amplifier applications, communication devices and network nodes are also disclosed.

Abstract: A quadrature phase detector circuit for a multi-antenna radio circuit comprising a plurality of frequency synthesizers using a common reference oscillator signal is disclosed.

Abstract: A transceiver arrangement comprises a receiver arranged for frequency-division duplex communication with a communication network; a transmitter arranged for frequency-division duplex communication with the communication network; an transmission port for connecting to an antenna; a balancing impedance circuit arranged to provide an adaptive impedance arranged to mimic the impedance at the transmission port; and a filtering arrangement, which comprises filters of a first type and filters of a second type, connecting the receiver, transmitter, transmission port and balancing impedance circuit. The filters of the first type are arranged to pass signals at transmitter frequency and attenuate signals at receiver frequency and are connected between the transmitter and the transmission port and between the receiver and the balancing impedance circuit.

Abstract: A digital solution for phase control of an output of a phase-locked loop (PLL) (100) is provided to achieve a desired phase shift at the output of the PLL (100). To that end, a fraction of the pulses of a PLL feedback signal are time shifted to achieve a desired average time shift associated with the desired phase shift. As a result, a desired phase shift is generated at the output of the PLL (100), while a desired devisor of the feedback signal is maintained on average. The resulting digital solution provides highly accurate phase control.

Abstract: A transceiver suitable for frequency division duplex (FDD) communication is disclosed. In one exemplary embodiment, a transmitter leakage reduction circuit for a transceiver is described. The transmitter leakage reduction circuit comprises an auxiliary power amplifier, first and second filters, and a signal transmission arrangement. The auxiliary power amplifier is configured to provide an auxiliary power amplifier output signal that represents an output signal of a power amplifier of the transmitter with a controllable phase shift or gain output. The first and second filters are configured to attenuate any signals in the receive frequency band of the respective power amplifier output signal and auxiliary power amplifier output signal. The signal transmission arrangement is configured to suppress a contribution of the power amplifier output signal from a signal received from an RF connecting point using the auxiliary power amplifier output signal to obtain a received signal that is input to the receiver.