Patents by Inventor Henry Chien

Henry Chien has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210013224
    Abstract: In the highly efficient fabrication processes for HNOR arrays provided herein, the channel regions of the storage transistors in the HNOR arrays are protected by a protective layer after deposition until the subsequent deposition of a charge-trapping material before forming local word lines. Both the silicon for the channel regions and the protective material may be deposited in amorphous form and are subsequently crystallized in an anneal step. The protective material may be silicon boron, silicon carbon or silicon germanium. The protective material induces greater grain boundaries in the crystallized silicon in the channel regions, thereby providing greater charge carrier mobility, greater conductivity and greater current densities.
    Type: Application
    Filed: July 9, 2020
    Publication date: January 14, 2021
    Applicant: SUNRISE MEMORY CORPORATION
    Inventors: Vinod Purayath, Wu-Yi Henry Chien
  • Publication number: 20200403002
    Abstract: A method addresses low cost, low resistance metal interconnects and mechanical stability in a high aspect ratio structure. According to the various implementations disclosed herein, a replacement metal process, which defers the need for a metal etching step in the fabrication process until after all patterned photoresist is no longer present. Under this process, the conductive sublayers may be both thick and numerous.
    Type: Application
    Filed: September 3, 2020
    Publication date: December 24, 2020
    Applicant: Sunrise Memory Corporation
    Inventors: Eli Harari, Scott Brad Herner, Wu-Yi Henry Chien
  • Publication number: 20200365609
    Abstract: A process forms thin-film storage transistors (e.g., HNOR devices) with improved channel regions by conformally depositing a thin channel layer in a cavity bordering a source region and a drain region, such that a portion of the channel material abuts by junction contact the source region and another portion of the channel layer abut by junction contact the drain region. The cavity is also bordered by a storage layer. In one form of the process, the channel region is formed before the storage layer is formed. In another form of the storage layer is formed before the channel region is formed.
    Type: Application
    Filed: May 15, 2020
    Publication date: November 19, 2020
    Applicant: Sunrise Memory Corporation
    Inventors: Eli Harari, Wu-Yi Henry Chien
  • Patent number: 10818692
    Abstract: A method addresses low cost, low resistance metal interconnects and mechanical stability in a high aspect ratio structure. According to the various implementations disclosed herein, a replacement metal process, which defers the need for a metal etching step in the fabrication process until after all patterned photoresist is no longer present. Under this process, the conductive sublayers may be both thick and numerous. The present invention also provides for a strut structure which facilitates etching steps on high aspect ratio structures, which enhances mechanical stability in a high aspect ratio memory stack.
    Type: Grant
    Filed: February 17, 2020
    Date of Patent: October 27, 2020
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Eli Harari, Scott Brad Herner, Wu-Yi Henry Chien
  • Publication number: 20200303414
    Abstract: A method to ease the fabrication of high aspect ratio three dimensional memory structures for memory cells with feature sizes of 20 nm or less, or with a high number of memory layers. The present invention also provides an improved isolation between adjacent memory cells along the same or opposite sides of an active strip. The improved isolation is provided by introducing a strong dielectric barrier film between adjacent memory cells along the same side of an active strip, and by staggering memory cells of opposite sides of the active strip.
    Type: Application
    Filed: June 5, 2020
    Publication date: September 24, 2020
    Applicant: SUNRISE MEMORY CORPORATION
    Inventors: Eli Harari, Wu-Yi Henry Chien, Scott Brad Herner
  • Publication number: 20200258897
    Abstract: A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer, and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.
    Type: Application
    Filed: February 10, 2020
    Publication date: August 13, 2020
    Applicant: Sunrise Memory Corporation
    Inventors: Tianhong Yan, Scott Brad Herner, Jie Zhou, Wu-Yi Henry Chien, Eli Harari
  • Publication number: 20200258903
    Abstract: A method addresses low cost, low resistance metal interconnects and mechanical stability in a high aspect ratio structure. According to the various implementations disclosed herein, a replacement metal process, which defers the need for a metal etching step in the fabrication process until after all patterned photoresist is no longer present. Under this process, the conductive sublayers may be both thick and numerous. The present invention also provides for a strut structure which facilitates etching steps on high aspect ratio structures, which enhances mechanical stability in a high aspect ratio memory stack.
    Type: Application
    Filed: February 17, 2020
    Publication date: August 13, 2020
    Applicant: Sunrise Memory Corporation
    Inventors: Eli Harari, Scott Brad Herner, Wu-Yi Henry Chien
  • Patent number: 10741581
    Abstract: A process for manufacturing a 3-dimensional memory structure includes: (a) providing one or more active layers over a planar surface of a semiconductor substrate, each active layer comprising (i) first and second semiconductor layers of a first conductivity; (ii) a dielectric layer separating the first and second semiconductor layer; and (ii) one or more sacrificial layers, at least one of sacrificial layers being adjacent the first semiconductor layer; (b) etching the active layers to create a plurality of active stacks and a first set of trenches each separating and exposing sidewalls of adjacent active stacks; (c) filling the first set of trenches by a silicon oxide; (d) patterning and etching the silicon oxide to create silicon oxide columns each abutting adjacent active stacks and to expose portions of one or more sidewalls of the active stacks; (e) removing the sacrificial layers from exposed portions of the sidewalls by isotropic etching through the exposed portions of the sidewalls of the active stack
    Type: Grant
    Filed: July 12, 2019
    Date of Patent: August 11, 2020
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Eli Harari, Scott Brad Herner, Wu-Yi Henry Chien
  • Patent number: 10741584
    Abstract: A method to ease the fabrication of high aspect ratio three dimensional memory structures for memory cells with feature sizes of 20 nm or less, or with a high number of memory layers. The present invention also provides an improved isolation between adjacent memory cells along the same or opposite sides of an active strip. The improved isolation is provided by introducing a strong dielectric barrier film between adjacent memory cells along the same side of an active strip, and by staggering memory cells of opposite sides of the active strip.
    Type: Grant
    Filed: March 4, 2020
    Date of Patent: August 11, 2020
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Eli Harari, Wu-Yi Henry Chien, Scott Brad Herner
  • Publication number: 20200203378
    Abstract: A method to ease the fabrication of high aspect ratio three dimensional memory structures for memory cells with feature sizes of 20 nm or less, or with a high number of memory layers. The present invention also provides an improved isolation between adjacent memory cells along the same or opposite sides of an active strip. The improved isolation is provided by introducing a strong dielectric barrier film between adjacent memory cells along the same side of an active strip, and by staggering memory cells of opposite sides of the active strip.
    Type: Application
    Filed: March 4, 2020
    Publication date: June 25, 2020
    Applicant: SUNRISE MEMORY CORPORATION
    Inventors: Eli Harari, Wu-Yi Henry Chien, Scott Brad Herner
  • Publication number: 20200185411
    Abstract: A method for forming 3-dimensional vertical NOR-type memory string arrays uses damascene local bit lines is provided. The method of the present invention also avoids ribboning by etching local word lines in two steps. By etching the local word lines in two steps, the aspect ratio in the patterning and etching of stack of local word lines (“word line stacks”) is reduced, which improves the structural stability of the word line stacks.
    Type: Application
    Filed: December 9, 2019
    Publication date: June 11, 2020
    Applicant: SUNRISE MEMORY CORPORATION
    Inventors: Scott Brad Herner, Wu-Yi Henry Chien, Jie Zhou, Eli Harari
  • Publication number: 20200176468
    Abstract: Various methods overcome the limitations and achieve superior scaling by (i) replacing a single highly challenging high aspect ratio etch step with two or more etch steps of less challenging aspect ratios and which involve wider and more mechanically stable active strips, (ii) using dielectric pillars for support and to maintain structural stability during a high aspect ratio etch step and subsequent processing steps, or (iii) using multiple masking steps to provide two or more etch steps of less challenging aspect ratios and which involve wider and more mechanically stable active strips.
    Type: Application
    Filed: December 4, 2019
    Publication date: June 4, 2020
    Applicant: SUNRISE MEMORY CORPORATION
    Inventors: Scott Brad Herner, Wu-Yi Henry Chien, Jie Zhou, Eli Harari
  • Patent number: 10622377
    Abstract: A method to ease the fabrication of high aspect ratio three dimensional memory structures for memory cells with feature sizes of 20 nm or less, or with a high number of memory layers. The present invention also provides an improved isolation between adjacent memory cells along the same or opposite sides of an active strip. The improved isolation is provided by introducing a strong dielectric barrier film between adjacent memory cells along the same side of an active strip, and by staggering memory cells of opposite sides of the active strip.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: April 14, 2020
    Assignee: SUNRISE MEMORY CORPORATION
    Inventors: Eli Harari, Wu-Yi Henry Chien, Scott Brad Herner
  • Publication number: 20200098779
    Abstract: Various methods and various staircase structures formed out of the active strips of a memory structure (e.g., a memory array having a three-dimensional arrangement of NOR memory strings) above a semiconductor substrate allows efficient electrical connections to semiconductor layers within the active strips.
    Type: Application
    Filed: September 20, 2019
    Publication date: March 26, 2020
    Applicant: SUNRISE MEMORY CORPORATION
    Inventors: Raul Adrian Cernea, Wu-Yi Henry Chien, Eli Harari
  • Publication number: 20200098789
    Abstract: A thin-film storage transistor includes (a) first and second semiconductor regions comprising polysilicon of a first conductivity; and (b) a channel region between the first and second semiconductor regions, the channel region comprising single-crystal epitaxial grown silicon, and wherein the thin-film storage transistor is formed above a monocrystalline semiconductor substrate.
    Type: Application
    Filed: September 23, 2019
    Publication date: March 26, 2020
    Applicant: SUNRISE MEMORY CORPORATION
    Inventors: Chenming Hu, Wu-Yi Henry Chien, Eli Harari
  • Publication number: 20200051990
    Abstract: A thin-film storage transistor includes (a) first and second polysilicon layers of a first conductivity serving, respectively, as a source terminal and a drain terminal of the thin-film storage transistor; (b) a third polysilicon layer of a second conductivity adjacent the first and second polysilicon layers, serving as a channel region of the thin-film storage transistor; (c) a conductor serving as a gate terminal of the thin-film storage transistor; and (d) a charge-trapping region between the conductor and third polysilicon layer, wherein a fourth body layer polysilicon of the second conductivity is included to provide an alternative source of free charge careers to accelerate device operation.
    Type: Application
    Filed: July 11, 2019
    Publication date: February 13, 2020
    Applicant: Sunrise Memory Corporation
    Inventors: Eli Harari, Raul Adrian Cernea, George Samachisa, Wu-Yi Henry Chien
  • Publication number: 20200020718
    Abstract: A process for manufacturing a 3-dimensional memory structure includes: (a) providing one or more active layers over a planar surface of a semiconductor substrate, each active layer comprising (i) first and second semiconductor layers of a first conductivity; (ii) a dielectric layer separating the first and second semiconductor layer; and (ii) one or more sacrificial layers, at least one of sacrificial layers being adjacent the first semiconductor layer; (b) etching the active layers to create a plurality of active stacks and a first set of trenches each separating and exposing sidewalls of adjacent active stacks; (c) filling the first set of trenches by a silicon oxide; (d) patterning and etching the silicon oxide to create silicon oxide columns each abutting adjacent active stacks and to expose portions of one or more sidewalls of the active stacks; (e) removing the sacrificial layers from exposed portions of the sidewalls by isotropic etching through the exposed portions of the sidewalls of the active stack
    Type: Application
    Filed: July 12, 2019
    Publication date: January 16, 2020
    Applicant: Sunrise Memory Corporation
    Inventors: Eli Harari, Scott Brad Herner, Wu-Yi Henry Chien
  • Publication number: 20190206890
    Abstract: A method to ease the fabrication of high aspect ratio three dimensional memory structures for memory cells with feature sizes of 20 nm or less, or with a high number of memory layers. The present invention also provides an improved isolation between adjacent memory cells along the same or opposite sides of an active strip. The improved isolation is provided by introducing a strong dielectric barrier film between adjacent memory cells along the same side of an active strip, and by staggering memory cells of opposite sides of the active strip.
    Type: Application
    Filed: December 21, 2018
    Publication date: July 4, 2019
    Applicant: SUNRISE MEMORY CORPORATION
    Inventors: Eli Harari, Wu-Yi Henry Chien, Scott Brad Herner
  • Patent number: 9870945
    Abstract: A stack of alternating layers comprising first epitaxial semiconductor layers and second epitaxial semiconductor layers is formed over a single crystalline substrate. The first and second epitaxial semiconductor layers are in epitaxial alignment with a crystal structure of the single crystalline substrate. The first epitaxial semiconductor layers include a first single crystalline semiconductor material, and the second epitaxial semiconductor layers include a second single crystalline semiconductor material that is different from the first single crystalline semiconductor material. A backside contact opening is formed through the stack, and backside cavities are formed by removing the first epitaxial semiconductor layers selective to the second epitaxial semiconductor layers. A stack of alternating layers including insulating layers and electrically conductive layers is formed. Each insulating layer contains a dielectric material portion deposited within a respective backside cavity.
    Type: Grant
    Filed: March 10, 2015
    Date of Patent: January 16, 2018
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jayavel Pachamuthu, Matthias Baenninger, Stephen Shi, Johann Alsmeier, Henry Chien
  • Patent number: RE47923
    Abstract: A PiP semiconductor device has an inner known good semiconductor package. In the semiconductor package, a first via is formed in a temporary carrier. A first conductive layer is formed over the carrier and into the first via. The first conductive layer in the first via forms a conductive bump. A first semiconductor die is mounted to the first conductive layer. A first encapsulant is deposited over the first die and carrier. The semiconductor package is mounted to a substrate. A second semiconductor die is mounted to the first conductive layer opposite the first die. A second encapsulant is deposited over the second die and semiconductor package. A second via is formed in the second encapsulant to expose the conductive bump. A second conductive layer is formed over the second encapsulant and into the second via. The second conductive layer is electrically connected to the second die.
    Type: Grant
    Filed: March 1, 2016
    Date of Patent: March 31, 2020
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Zigmund R. Camacho, Frederick R. Dahilig, Lionel Chien Hui Tay, Arnel Senosa Trasporto, Henry Descalzo Bathan