Abstract: A method for forming 3-dimensional vertical NOR-type memory string arrays uses damascene local bit lines is provided. The method of the present invention also avoids ribboning by etching local word lines in two steps. By etching the local word lines in two steps, the aspect ratio in the patterning and etching of stack of local word lines (“word line stacks”) is reduced, which improves the structural stability of the word line stacks.

Abstract: In the highly efficient fabrication processes for HNOR arrays provided herein, the channel regions of the storage transistors in the HNOR arrays are protected by a protective layer after deposition until the subsequent deposition of a charge-trapping material before forming local word lines. Both the silicon for the channel regions and the protective material may be deposited in amorphous form and are subsequently crystallized in an anneal step. The protective material may be silicon boron, silicon carbon or silicon germanium. The protective material induces greater grain boundaries in the crystallized silicon in the channel regions, thereby providing greater charge carrier mobility, greater conductivity and greater current densities.

Abstract: A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.

Abstract: Thin-film Ferroelectric field-effect transistor (FeFET) may be organized as 3-dimensional NOR memory string arrays. Each 3-dimensional NOR memory string array includes a row of active stack each including a predetermined number of active strips each provided one on top of another and each being spaced apart from another by an isolation layer. Each active strip may include a shared source layer and a shared drain layer shared by the FeFETs provided along the active strip. Data storage in the active strip is provided by ferroelectric elements that can individually electrically set into one of two polarization states. FeFETs on separate active strips may be configured for read, programming or erase operations in parallel.

Abstract: A process includes (a) providing a semiconductor substrate having a planar surface; (b) forming a plurality of thin-film layers above the planar surface of the semiconductor substrate, one on top of another, including among the thin-film layers first and second isolation layers, wherein a significantly greater concentration of a first dopant specie is provided in the first isolation layer than in the second isolation layer; (c) etching along a direction substantially orthogonal to the planar surface through the thin-films to create a trench having sidewalls that expose the thin-film layers; (d) depositing conformally a semiconductor material on the sidewalls of the trench; (e) annealing the first isolation layer at a predetermined temperature and a predetermined duration such that the first isolation layer act as a source of the first dopant specie which dopes a portion of the semiconductor material adjacent the first isolation layer; and (f) selectively etching the semiconductor material to remove the doped

Abstract: A method for forming 3-dimensional vertical NOR-type memory string arrays uses damascene local bit lines is provided. The method of the present invention also avoids ribboning by etching local word lines in two steps. By etching the local word lines in two steps, the aspect ratio in the patterning and etching of stack of local word lines (“word line stacks”) is reduced, which improves the structural stability of the word line stacks.

Abstract: Thin-film Ferroelectric field-effect transistor (FeFET) may be organized as 3-dimensional NOR memory string arrays. Each 3-dimensional NOR memory string array includes a row of active stack each including a predetermined number of active strips each provided one on top of another and each being spaced apart from another by an isolation layer. Each active strip may include a shared source layer and a shared drain layer shared by the FeFETs provided along the active strip. Data storage in the active strip is provided by ferroelectric elements that can individually electrically set into one of two polarization states. FeFETs on separate active strips may be configured for read, programming or erase operations in parallel.

Abstract: A method addresses low cost, low resistance metal interconnects and mechanical stability in a high aspect ratio structure. According to the various implementations disclosed herein, a replacement metal process, which defers the need for a metal etching step in the fabrication process until after all patterned photoresist is no longer present. Under this process, the conductive sublayers may be both thick and numerous. The present invention also provides for a strut structure which facilitates etching steps on high aspect ratio structures, which enhances mechanical stability in a high aspect ratio memory stack.

Abstract: A thin-film memory transistor includes a source region, a drain region, a channel region, a gate electrode, and a charge-trapping layer provided between the channel region and the gate electrode and electrically isolated therefrom, wherein the charge-trapping layer has includes a number of charge-trapping sites that is 70% occupied or evacuated using a single voltage pulse of a predetermined width of 500 nanoseconds or less and a magnitude of 15.0 volts or less. The charge-trapping layer comprises silicon-rich nitride may have a refractive index of 2.05 or greater or comprises nano-crystals of germanium (Ge), zirconium oxide (ZrO2), or zinc oxide (ZnO). The thin-film memory transistor may be implemented, for example, in a 3-dimensional array of NOR memory strings formed above a planar surface of a semiconductor substrate.

Abstract: In the highly efficient fabrication processes for HNOR arrays provided herein, the channel regions of the storage transistors in the HNOR arrays are protected by a protective layer after deposition until the subsequent deposition of a charge-trapping material before forming local word lines. Both the silicon for the channel regions and the protective material may be deposited in amorphous form and are subsequently crystallized in an anneal step. The protective material may be silicon boron, silicon carbon or silicon germanium. The protective material induces greater grain boundaries in the crystallized silicon in the channel regions, thereby providing greater charge carrier mobility, greater conductivity and greater current densities.

Abstract: A process forms thin-film storage transistors (e.g., HNOR devices) with improved channel regions by conformally depositing a thin channel layer in a cavity bordering a source region and a drain region, such that a portion of the channel material abuts by junction contact the source region and another portion of the channel layer abut by junction contact the drain region. The cavity is also bordered by a storage layer. In one form of the process, the channel region is formed before the storage layer is formed. In another form of the storage layer is formed before the channel region is formed.

Abstract: A memory circuit includes: (i) a semiconductor substrate having a planar surface, the semiconductor substrate having formed therein circuitry for memory operations; (ii) a memory array formed above the planar surface, the memory array having one or more electrodes to memory circuits in the memory array, the conductors each extending along a direction substantially parallel to the planar surface; and (iii) one or more transistors each formed above, alongside or below a corresponding one of the electrodes but above the planar surface of the semiconductor substrate, each transistor (a) having first and second drain/source region and a gate region each formed out of a semiconductor material, wherein the first drain/source region, the second drain/source region or the gate region has formed thereon a metal silicide layer; and (b) selectively connecting the corresponding electrode to the circuitry for memory operations.

Abstract: A memory structure includes storage transistors organized as horizontal NOR memory strings where the storage transistors are thin-film ferroelectric field-effect transistors (FeFETs) having a ferroelectric gate dielectric layer formed adjacent an oxide semiconductor channel region. The ferroelectric storage transistors thus formed are junctionless transistors having no p/n junction in the channel. In some embodiments, the ferroelectric storage transistors in each NOR memory string share a common source line and a common bit line, the common source line and the common bit line formed on a first side of the channel region and the ferroelectric gate dielectric layer and in electrical contact with the oxide semiconductor channel region. The ferroelectric storage transistors in a NOR memory string are controlled by individual control gate electrodes formed on a second side, opposite the first side, of the ferroelectric gate dielectric layer.

Abstract: A memory structure includes storage transistors organized as horizontal NOR memory strings where the storage transistors are thin-film ferroelectric field-effect transistors (FeFETs) having a ferroelectric gate dielectric layer formed adjacent an oxide semiconductor channel region. The ferroelectric storage transistors thus formed are junctionless transistors having no p/n junction in the channel. In some embodiments, the ferroelectric storage transistors in each NOR memory string share a common source line and a common bit line that are formed on a first side of the channel region, away from the ferroelectric gate dielectric layer, and in electrical contact with the oxide semiconductor channel region. The ferroelectric storage transistors in a NOR memory string are controlled by individual control gate electrodes that are formed adjacent the ferroelectric gate dielectric layer on a second side, opposite the first side, of the channel region.

Abstract: A process includes (a) providing a semiconductor substrate having a planar surface; (b) forming a plurality of thin-film layers above the planar surface of the semiconductor substrate, one on top of another, including among the thin-film layers first and second isolation layers, wherein a significantly greater concentration of a first dopant specie is provided in the first isolation layer than in the second isolation layer; (c) etching along a direction substantially orthogonal to the planar surface through the thin-films to create a trench having sidewalls that expose the thin-film layers; (d) depositing conformally a semiconductor material on the sidewalls of the trench; (e) annealing the first isolation layer at a predetermined temperature and a predetermined duration such that the first isolation layer act as a source of the first dopant specie which dopes a portion of the semiconductor material adjacent the first isolation layer; and (f)selectively etching the semiconductor material to remove the doped p

Abstract: A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band of the charge-trapping layer has a value between ?1.0 eV and 2.3 eV. The storage transistor may further include a barrier layer between the tunnel dielectric layer and the charge-trapping layer, the barrier layer having a conduction band offset less than the conduction band offset of the charge-trapping layer.

Abstract: Thin-film Ferroelectric field-effect transistor (FeFET) may be organized as 3-dimensional NOR memory string arrays. Each 3-dimensional NOR memory string array includes a row of active stack each including a predetermined number of active strips each provided one on top of another and each being spaced apart from another by an isolation layer. Each active strip may include a shared source layer and a shared drain layer shared by the FeFETs provided along the active strip. Data storage in the active strip is provided by ferroelectric elements that can individually electrically set into one of two polarization states. FeFETs on separate active strips may be configured for read, programming or erase operations in parallel.

Abstract: A thin-film storage transistor includes (a) first and second semiconductor regions comprising polysilicon of a first conductivity; and (b) a channel region between the first and second semiconductor regions, the channel region comprising single-crystal epitaxial grown silicon, and wherein the thin-film storage transistor is formed above a monocrystalline semiconductor substrate.

Abstract: A storage transistor has a tunnel dielectric layer and a charge-trapping layer between a channel region and a gate electrode, wherein the charge-tapping layer has a conduction band offset that is less than the lowering of the tunneling barrier in the tunnel dielectric layer when a programming voltage is applied, such that electrons direct tunnel into the charge-trapping layer. The conduction band of the charge-trapping layer is has a value between ?1.0 eV and 2.3 eV. The storage transistor may further include a barrier layer between the tunnel dielectric layer and the charge-trapping layer, the barrier layer having a conduction band offset less than the conduction band offset of the charge-trapping layer.

Abstract: A process includes (a) providing a semiconductor substrate having a planar surface; (b) forming a plurality of thin-film layers above the planar surface of the semiconductor substrate, one on top of another, including among the thin-film layers first and second isolation layers, wherein a significantly greater concentration of a first dopant specie is provided in the first isolation layer than in the second isolation layer; (c) etching along a direction substantially orthogonal to the planar surface through the thin-films to create a trench having sidewalls that expose the thin-film layers; (d) depositing conformally a semiconductor material on the sidewalls of the trench; (e) annealing the first isolation layer at a predetermined temperature and a predetermined duration such that the first isolation layer act as a source of the first dopant specie which dopes a portion of the semiconductor material adjacent the first isolation layer; and (f) selectively etching the semiconductor material to remove the doped