Abstract: A method of forming a three-dimensional memory device, includes forming a lower stack structure of insulating and first sacrificial material layers over a substrate, forming first memory openings through the lower stack structure and filling the first memory openings with a sacrificial fill material, replacing the first sacrificial material layers with first electrically conductive layers, forming an upper stack structure of insulating and second sacrificial material layers over the lower stack structure after replacing the first sacrificial material layers, forming second memory openings through the upper stack structure in areas overlying the first memory openings, replacing the second sacrificial material layers with second electrically conductive layers, removing the sacrificial fill material from the first memory openings underneath the second memory openings to form inter-stack memory openings after replacing the second sacrificial material layers, and forming memory stack structures within the inter-st

Abstract: A first stack of alternating layers including first electrically conductive layers and first electrically insulating layers is formed with first stepped surfaces and a first dielectric material portion thereupon. Dielectric pillar structures including a dielectric metal oxide can be formed through the first stepped surfaces. Lower memory openings can be formed, and filled with a disposable material or a lower memory opening structure including a lower semiconductor channel and a doped semiconductor region. At least one dielectric material layer and a second stack of alternating layers including second electrically conductive layers and second electrically insulating layers can be sequentially formed. Upper memory openings can be formed through the second stack and the at least one dielectric material layer. A memory film and a semiconductor channel can be formed after removal of the disposable material, or an upper semiconductor channel can be formed on the doped semiconductor region.

Abstract: A memory stack structure for a three-dimensional device includes an alternating stack of insulator layers and spacer material layers. A memory opening is formed through the alternating stack. A memory material layer, a tunneling dielectric layer, and a silicon oxide liner are formed in the memory opening. A sacrificial liner is subsequently formed over the tunneling dielectric layer. The layer stack is anisotropically etched to physically expose a semiconductor surface of the substrate underneath the memory opening. The sacrificial liner may be removed prior to, or after, the anisotropic etch. The silicon oxide liner is removed after the anisotropic etch. A semiconductor channel layer can be deposited directly on the tunneling dielectric layer as a single material layer without any interface therein.

Abstract: Peripheral devices for a three-dimensional memory device can be formed over an array of memory stack structures to increase areal efficiency of a semiconductor chip. First contact via structures and first metal lines are formed over an array of memory stack structures and an alternating stack of insulating layers and electrically conductive layers. A semiconductor material layer including a single crystalline semiconductor material or a polycrystalline semiconductor material is formed over first metal lines. After formation of semiconductor devices on or in the semiconductor material layer, metal interconnect structures including second metal lines and additional conductive via structures are formed to electrically connect nodes of the semiconductor devices to respective first metal lines and to memory devices underneath.

Abstract: A method of fabricating a semiconductor device, such as a three-dimensional NAND memory string, includes forming a carbon etch stop layer having a first width over a major surface of a substrate, forming a stack of alternating material layers over the etch stop layer, etching the stack to the etch stop layer to form a memory opening having a second width at a bottom of the memory opening that is smaller than the width of the etch stop layer, removing the etch stop layer to provide a void area having a larger width than the second width of the memory opening, forming a memory film over a sidewall of the memory opening and in the void area, and forming a semiconductor channel in the memory opening such that the memory film is located between the semiconductor channel and the sidewall of the memory opening.

Abstract: A monolithic three dimensional NAND string including a stack of alternating first material layers and second material layers different from the first material layers over a major surface of a substrate. The first material layers include a plurality of control gate electrodes and the second material layers include an insulating material and the plurality of control gate electrodes extend in a first direction. The NAND string also includes a semiconductor channel, a blocking dielectric, and a plurality of vertically spaced apart floating gates. Each of the plurality of vertically spaced apart floating gates or each of the second material layers includes a first portion having a first thickness in the second direction, and a second portion adjacent to the first portion in the first direction and having a second thickness in the second direction which is different than the first thickness.

Abstract: A method of making a vertical NAND device includes forming a lower portion of a memory stack over a substrate, forming a lower portion of memory openings in the lower portion of the memory stack, and at least partially filling the lower portion of the memory openings with a sacrificial material. The method also includes forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material, forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings, removing the sacrificial material to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings, and forming a semiconductor channel in each continuous memory opening.

Abstract: A vertical NAND string device includes a semiconductor channel, where at least one end portion of the semiconductor channel extends substantially perpendicular to a major surface of a substrate, at least one semiconductor or electrically conductive landing pad embedded in the semiconductor channel, a tunnel dielectric located adjacent to the semiconductor channel, a charge storage region located adjacent to the tunnel dielectric, a blocking dielectric located adjacent to the charge storage region and a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate.

Abstract: Techniques for forming 3D memory arrays are disclosed. Memory openings are filled with a sacrificial material, such as silicon or nitride. Afterwards, a replacement technique is used to remove nitride from an ONON stack and replace it with a conductive material such as tungsten. Afterwards, memory cell films are formed in the memory openings. The conductive material serves as control gates of the memory cells. The control gate will not suffer from corner rounding. ONON shrinkage is avoided, which will prevent control gate shrinkage. Block oxide between the charge storage region and control gate may be deposited after control gate replacement, so the uniformity is good. Block oxide may be deposited after control gate replacement, so TiN adjacent to control gates can be thicker to prevent fluorine attacking the insulator between adjacent control gates. Therefore, control gate to control gate shorting is prevented.

Abstract: A multi-tier memory device is formed over a substrate such that memory stack structures extend through an alternating stack of insulating layers and electrically conductive layers within each tier. Bit lines are formed between an underlying tier having drain regions over semiconductor channels and an overlying tier having drain regions under semiconductor channel, such that the bit lines are shared between the underlying tier and the overlying tier. Source lines can be formed over each tier in which source regions overlie semiconductor channels and drain regions. If another tier is present above the source lines, the source lines can be shared between two vertically neighboring tiers.

Abstract: A reversible resistance-switching memory cell has multiple narrow, spaced apart bottom electrode structures. The raised structures can be formed by coating a bottom electrode layer with nano-particles and etching the bottom electrode layer. The raised structures can be independent or joined to one another at a bottom of the bottom electrode layer. A resistance-switching material is provided between and above the bottom electrode structure, followed by a top electrode layer. Or, insulation is provided between and above the bottom electrode structures, and the resistance-switching material and top electrode layer are above the insulation. Less than one-third of a cross-sectional area of each resistance-switching memory cell is consumed by the one or more raised structures. When the resistance state of the memory cell is switched, there is a smaller area in the bottom electrode for a current path, so the switching resistance is higher and the switching current is lower.

Abstract: A method of making a vertical NAND device includes forming a lower portion of a memory stack over a substrate, forming a lower portion of memory openings in the lower portion of the memory stack, and forming a sacrificial material portion including an encapsulated cavity. The method also includes forming an upper portion of the memory stack over the lower portion of the memory stack and over the sacrificial material, forming an upper portion of the memory openings in the upper portion of the memory stack to expose the sacrificial material in the lower portion of the memory openings, removing the sacrificial material portion to connect the lower portion of the memory openings with a respective upper portion of the memory openings to form continuous memory openings, and forming a semiconductor channel in each continuous memory opening.

Abstract: A method includes forming an amorphous or polycrystalline semiconductor material over at least a portion of a sidewall of a front side opening and within front side recesses in a stack of alternating first and second material layers, forming a layer of a metal material over at least a portion of the sidewall of the front side opening and adjacent to the semiconductor material within the front side recesses; annealing the metal material and the semiconductor material within the front side recesses to form a large grain polycrystalline or single crystal semiconductor material charge storage region within each of the front side recesses by a metal induced crystallization process, and forming a tunnel dielectric layer and semiconductor channel in the front side opening. Following the metal induced crystallization process, at least a portion of the metal material is located between the charge storage regions and the second material layers.

Abstract: A stack of alternating layers comprising first epitaxial semiconductor layers and second epitaxial semiconductor layers is formed over a single crystalline substrate. The first and second epitaxial semiconductor layers are in epitaxial alignment with a crystal structure of the single crystalline substrate. The first epitaxial semiconductor layers include a first single crystalline semiconductor material, and the second epitaxial semiconductor layers include a second single crystalline semiconductor material that is different from the first single crystalline semiconductor material. A backside contact opening is formed through the stack, and backside cavities are formed by removing the first epitaxial semiconductor layers selective to the second epitaxial semiconductor layers. A stack of alternating layers including insulating layers and electrically conductive layers is formed. Each insulating layer contains a dielectric material portion deposited within a respective backside cavity.

Abstract: In a fabrication process for reversible resistance-switching memory cells, a bottom electrode layer is coated with nano-particles. The nano-particles are used to etch the bottom electrode layer, forming multiple narrow, spaced apart bottom electrode structures for each memory cell. A resistance-switching material is then deposited between and above the bottom electrode structures, followed by a top electrode layer. Or, insulation is deposited between and above the bottom electrode structures, followed by planarizing and a wet etch to expose top surfaces of the bottom electrode structures, then deposition of the resistance-switching material and the top electrode layer. When the resistance state of the memory cell is switched, there is a smaller area in the bottom electrode for a current path, so the switching resistance is higher and the switching current is lower.

Abstract: High-density semiconductor memory utilizing metal control gate structures and air gap electrical isolation between discrete devices in these types of structures are provided. During gate formation and definition, etching the metal control gate layer(s) is separated from etching the charge storage layer to form protective sidewall spacers along the vertical sidewalls of the metal control gate layer(s). The sidewall spacers encapsulate the metal control gate layer(s) while etching the charge storage material to avoid contamination of the charge storage and tunnel dielectric materials. Electrical isolation is provided, at least in part, by air gaps that are formed in the row direction and/or air gaps that are formed in the column direction.

Abstract: A method of making a monolithic three dimensional NAND string includes forming a stack of alternating first and second material layers over a substrate, etching the stack to form a front side opening, partially removing the second material layers through the front side opening to form front side recesses, forming a first blocking dielectric in the front side recesses, forming charge storage regions over the first blocking dielectric in the front side recesses, forming a tunnel dielectric layer and a semiconductor channel over the charge storage regions in the front side opening, etching the stack to form a back side opening, removing the second material layers through the back side opening to form back side recesses using the first blocking dielectric as an etch stop, forming a second blocking dielectric in the back side recesses, and forming control gates over the second blocking dielectric in the back side recesses.

Abstract: A memory device and a method of making a memory device that includes a semiconductor channel, a tunnel dielectric layer located over the semiconductor channel, a floating gate located over the tunnel dielectric layer, the floating gate comprising a continuous layer of an electrically conductive material and at least one protrusion of an electrically conductive material facing the tunnel dielectric layer and electrically shorted to the continuous layer, a blocking dielectric region located over the floating gate, and a control gate located over the blocking dielectric layer.

Abstract: Monolithic three-dimensional NAND memory strings and methods of fabricating a monolithic three-dimensional NAND memory string include forming single crystal or large grain polycrystalline semiconductor material charge storage regions by a metal induced crystallization process. In another embodiment, a plurality of front side recesses are formed having a concave-shaped surface and a blocking dielectric and charge storage regions are formed within the front side recesses and over the concave-shaped surface. In another embodiment, layers of oxide material exposed in a front side opening of a material layer stack are surface nitrided and etched to provide convexly-rounded corner portions, and a blocking dielectric is formed over the convexly-rounded corner portions.

Abstract: A first stack of alternating layers including first electrically conductive layers and first electrically insulating layers is formed with first stepped surfaces and a first dielectric material portion thereupon. Dielectric pillar structures including a dielectric metal oxide can be formed through the first stepped surfaces. Lower memory openings can be formed, and filled with a disposable material or a lower memory opening structure including a lower semiconductor channel and a doped semiconductor region. At least one dielectric material layer and a second stack of alternating layers including second electrically conductive layers and second electrically insulating layers can be sequentially formed. Upper memory openings can be formed through the second stack and the at least one dielectric material layer. A memory film and a semiconductor channel can be formed after removal of the disposable material, or an upper semiconductor channel can be formed on the doped semiconductor region.