Patents by Inventor Henry D. Bathan

Henry D. Bathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230197583
    Abstract: A semiconductor device has a substrate and leads formed on two or more sides of the substrate. An electrical component is disposed over the substrate and electrically connected to the lead with bumps or bond wires. The electrical component is encapsulated. A portion of the substrate is removed to form a wettable flank on at least three sides of the lead. The substrate has a molding compound and the lead is disposed within or adjacent to the molding compound. A portion of the molding compound can remain at corners of the substrate. The lead has a first surface or recessed surface on a first side of the lead, a second surface or recessed surface on a second side of the lead, and a third surface or recessed surface on a third side of the lead. A portion of a surface of the lead is plated.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 22, 2023
    Applicant: Semtech Corporation
    Inventors: Henry D. Bathan, Yingyu Chen
  • Patent number: 9721925
    Abstract: A semiconductor device is made by forming first and second interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structures. An encapsulant is deposited over the first and second die and first, second, and third interconnect structures. A backside of the second die is substantially coplanar with the first interconnect structure and a backside of the first semiconductor die is substantially coplanar with the third interconnect structure. The first interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the second die. The third interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the first die.
    Type: Grant
    Filed: October 14, 2014
    Date of Patent: August 1, 2017
    Assignee: STATS ChipPAC, Pte. Ltd.
    Inventors: Henry D. Bathan, Zigmund R. Camacho, Jairus L. Pisigan
  • Patent number: 9589876
    Abstract: A semiconductor device is made by forming solder bumps over a copper carrier. Solder capture indentations are formed in the copper carrier to receive the solder bumps. A semiconductor die is mounted to the copper carrier using a die attach adhesive. The semiconductor die has contact pads formed over its active surface. An encapsulant is deposited over the copper carrier, solder bumps, and semiconductor die. A portion of the encapsulant is removed to expose the solder bumps and contact pads. A conductive layer is formed over the encapsulant to connect the solder bumps and contact pads. The conductive layer operates as a redistribution layer to route electrical signals from the solder bumps to the contact pads. The copper carrier is removed. An insulating layer is formed over the conductive layer and encapsulant. A plurality of semiconductor devices can be stacked and electrically connected through the solder bumps.
    Type: Grant
    Filed: August 27, 2013
    Date of Patent: March 7, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Zigmund R. Camacho, Lionel Chien Hui Tay, Henry D. Bathan, Dioscoro A. Merilo, Jeffrey D. Punzalan
  • Patent number: 9525080
    Abstract: A semiconductor device includes a carrier and semiconductor die having an optically active region. The semiconductor die is mounted to the carrier to form a separation between the carrier and the semiconductor die. The semiconductor device further includes a passivation layer disposed over a surface of the semiconductor die and a glass layer disposed over a surface of the passivation layer. The passivation layer has a clear portion for passage of light to the optically active region of the semiconductor die. The semiconductor device further includes an encapsulant disposed over the carrier within the separation to form an expansion region around a periphery of the semiconductor die, a first via penetrating the expansion region, glass layer, and passivation layer, a second via penetrating the glass layer and passivation layer to expose a contact pad on the semiconductor die, and a conductive material filling the first and second vias.
    Type: Grant
    Filed: July 23, 2012
    Date of Patent: December 20, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Zigmund R. Camacho, Henry D. Bathan, Lionel Chien Hui Tay, Arnel Senosa Trasporto
  • Patent number: 9472427
    Abstract: A semiconductor device has a leadframe with first and second opposing surfaces and a plurality of notched fingers. The leadframe is mounted to a carrier. A first semiconductor die is mounted over the carrier between the notched fingers. Conductive TSVs are formed through the first semiconductor die. A bond wire is formed between a first contact pad on the first semiconductor die and notched finger. The conductive TSV are electrically connected to the bond wires. An encapsulant is deposited over the first semiconductor die and notched fingers. Bumps are formed over the first surface of the leadframe. The carrier is removed and the leadframe is singulated. The leadframe and first semiconductor die is mounted to a substrate. A second semiconductor die is mounted to a second contact pad on the first semiconductor die. A third semiconductor die is mounted to the second surface of the leadframe.
    Type: Grant
    Filed: March 22, 2011
    Date of Patent: October 18, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Henry D. Bathan, Zigmund R. Camacho, Jairus L. Pisigan
  • Patent number: 9397236
    Abstract: A semiconductor device is made by providing a semiconductor die having an optically active area, providing a leadframe or pre-molded laminated substrate having a plurality of contact pads and a light transmitting material disposed between the contact pads, attaching the semiconductor die to the leadframe so that the optically active area is aligned with the light transmitting material to provide a light transmission path to the optically active area, and disposing an underfill material between the semiconductor die and leadframe. The light transmitting material includes an elevated area to prevent the underfill material from blocking the light transmission path. The elevated area includes a dam surrounding the light transmission path, an adhesive ring, or the light transmission path itself can be the elevated area. An adhesive ring can be disposed on the dam. A filler material can be disposed between the light transmitting material and contact pads.
    Type: Grant
    Filed: September 9, 2013
    Date of Patent: July 19, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Zigmund R. Camacho, Henry D. Bathan, Lionel Chien Hui Tay, Arnel Senosa Trasporto
  • Patent number: 9129971
    Abstract: A semiconductor device includes a semiconductor die having contact pads disposed over a surface of the semiconductor die, a die attach adhesive layer disposed under the semiconductor die, and an encapsulant material disposed around and over the semiconductor die. The semiconductor device further includes bumps disposed in the encapsulant material around a perimeter of the semiconductor die. The bumps are partially enclosed by the encapsulant material. The semiconductor device further comprises first vias disposed in the encapsulant. The first vias expose surfaces of the contact pads. The semiconductor device further includes a first redistribution layer (RDL) disposed over the encapsulant and in the first vias, and a second RDL disposed under the encapsulant material and the die attach adhesive layer. The first RDL electrically connects each contact pad of the semiconductor die to one of the bumps, and the second RDL is electrically connected to one of the bumps.
    Type: Grant
    Filed: January 6, 2011
    Date of Patent: September 8, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Zigmund R. Camacho, Lionel Chien Hui Tay, Henry D. Bathan, Jeffrey D. Punzalan
  • Patent number: 9006031
    Abstract: A semiconductor device has a carrier with a die attach area. Recesses are formed partially through the carrier outside the die attach area. A first conductive layer is conformally applied over a surface of the carrier and into the recesses. A semiconductor die is mounted to the die attach area of the carrier. An encapsulant is deposited over the carrier and semiconductor die. The encapsulant extends into the recesses over the first conductive layer to form encapsulant bumps. The carrier is removed to expose the first conductive layer over the encapsulant bumps. A first insulating layer is formed over the semiconductor die with openings to expose contact pads of the semiconductor die. A second conductive layer is formed between the first conductive layer and the contact pads on the semiconductor die. A second insulating layer is formed over the second conductive layer and semiconductor die.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: April 14, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Zigmund R. Camacho, Henry D. Bathan, Emmanuel A. Espiritu
  • Patent number: 8993376
    Abstract: A semiconductor device has a base substrate with first and second opposing surfaces. A plurality of cavities and base leads between the cavities is formed in the first surface of the base substrate. The first set of base leads can have a different height or similar height as the second set of base leads. A concave capture pad can be formed over the second set of base leads. Alternatively, a plurality of openings can be formed in the base substrate and the semiconductor die mounted to the openings. A semiconductor die is mounted between a first set of the base leads and over a second set of the base leads. An encapsulant is deposited over the die and base substrate. A portion of the second surface of the base substrate is removed to separate the base leads. An interconnect structure is formed over the encapsulant and base leads.
    Type: Grant
    Filed: October 28, 2011
    Date of Patent: March 31, 2015
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Zigmund R. Camacho, Emmanuel A. Espiritu, Henry D. Bathan, Dioscoro A. Merilo
  • Publication number: 20150028496
    Abstract: A semiconductor device is made by forming first and second interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structures. An encapsulant is deposited over the first and second die and first, second, and third interconnect structures. A backside of the second die is substantially coplanar with the first interconnect structure and a backside of the first semiconductor die is substantially coplanar with the third interconnect structure. The first interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the second die. The third interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the first die.
    Type: Application
    Filed: October 14, 2014
    Publication date: January 29, 2015
    Applicant: STATS CHIPPAC, LTD.
    Inventors: Henry D. Bathan, Zigmund R. Camacho, Jairus L. Pisigan
  • Patent number: 8921983
    Abstract: A semiconductor device includes a first semiconductor die. A plurality of conductive vias is formed around the first semiconductor die. A first conductive layer is formed over a first surface of the first semiconductor die and electrically connects to the plurality of conductive vias. A second conductive layer is formed over a second surface of the first semiconductor die opposite the first surface and electrically connects to the plurality of conductive vias. A first passivation layer is formed over the first surface and includes openings that expose the first conductive layer. A second passivation layer is formed over the second surface and includes openings that expose the second conductive layer. Bonding pads are formed within the openings in the first and second passivation layers and are electrically connected to the first and second conductive layers. An interconnect structure is disposed within the openings in the first and second passivation layers.
    Type: Grant
    Filed: September 18, 2011
    Date of Patent: December 30, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Lionel Chien Hui Tay, Henry D. Bathan, Zigmund R. Camacho
  • Patent number: 8872320
    Abstract: A semiconductor device is made by forming first and interconnect structures over a first semiconductor die. A third interconnect structure is formed in proximity to the first die. A second semiconductor die is mounted over the second and third interconnect structures. An encapsulant is deposited over the first and second die and first, second, and third interconnect structures. A backside of the second die is substantially coplanar with the first interconnect structure and a backside of the first semiconductor die is substantially coplanar with the third interconnect structure. The first interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the second die. The third interconnect structure has a height which is substantially the same as a combination of a height of the second interconnect structure and a thickness of the first die.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: October 28, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Henry D. Bathan, Zigmund R. Camacho, Jairus L. Pisigan
  • Patent number: 8866275
    Abstract: A semiconductor device has a substrate with a plurality of conductive vias formed through the substrate and first conductive layer formed over the substrate. A first semiconductor die is mounted over the substrate. A second semiconductor die can be mounted over the first semiconductor die. A leadframe interposer has a base plate and a plurality of base leads extending from the base plate. An etch-resistant conductive layer is formed over a surface of the base plate opposite the base leads. The leadframe is mounted to the substrate over the first semiconductor die. An encapsulant is deposited over the substrate and first semiconductor die. The base plate is removed while retaining the etch-resistant conductive layer and portion of the base plate opposite the base leads to electrically isolate the base leads. An interconnect structure is formed over a surface of the substrate opposite the base leads.
    Type: Grant
    Filed: February 13, 2013
    Date of Patent: October 21, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Zigmund R. Camacho, Dioscoro A. Merilo, Henry D. Bathan, Emmanuel A. Espiritu
  • Patent number: 8866248
    Abstract: A semiconductor device includes a carrier and semiconductor die having an optically active region. The semiconductor die is mounted to the carrier to form a separation between the carrier and the semiconductor die. The semiconductor device further includes a passivation layer disposed over a surface of the semiconductor die and a glass layer disposed over a surface of the passivation layer. The passivation layer has a clear portion for passage of light to the optically active region of the semiconductor die. The semiconductor device further includes an encapsulant disposed over the carrier within the separation to form an expansion region around a periphery of the semiconductor die, a first via penetrating the expansion region, glass layer, and passivation layer, a second via penetrating the glass layer and passivation layer to expose a contact pad on the semiconductor die, and a conductive material filling the first and second vias.
    Type: Grant
    Filed: November 8, 2010
    Date of Patent: October 21, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Zigmund R. Camacho, Henry D. Bathan, Lionel Chien Hui Tay, Arnel Senosa Trasporto
  • Patent number: 8802505
    Abstract: A semiconductor device is made by forming solder bumps on a first side of a semiconductor wafer. A protective layer is formed on a second side of the semiconductor wafer opposite the first side. The protective layer can be adhesive paste, laminated film, spin-coated resin, epoxy based elastomer, organic rubbery material, polystyrene, polyethylene terephthalate, or other polymer material. The semiconductor wafer is singulated into semiconductor die. The semiconductor die is mounted to a carrier. A molding compound is formed around the semiconductor die. The protective layer provides stress relief for the semiconductor die. The protective layer is removed from the semiconductor die. The protective layer can provide a thermal dissipation, in which case it is made with metal or polymer-based material with a filler such as alumina, zinc oxide, silicon dioxide, silver, aluminum, and aluminum nitride.
    Type: Grant
    Filed: September 30, 2008
    Date of Patent: August 12, 2014
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Henry D. Bathan, Zigmund R. Camacho, Jairus L. Pisigan
  • Patent number: 8633578
    Abstract: An integrated circuit package system with laminate base includes: a base package including: a laminate substrate strip, an integrated circuit on the laminate substrate strip, a molded cover over the integrated circuit and the laminate substrate strip, and a strip test of the base package; a bare die on the base package; the bare die electrically connected to the laminate substrate strip; and the bare die and the base package encapsulated.
    Type: Grant
    Filed: August 2, 2011
    Date of Patent: January 21, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry D. Bathan, Arnel Trasporto, Jeffrey D. Punzalan
  • Patent number: 8629537
    Abstract: An integrated circuit package system is provided forming a die support system from a padless lead frame having die supports with each substantially equally spaced from another, and attaching an integrated circuit die having a peripheral area on the die supports.
    Type: Grant
    Filed: January 23, 2006
    Date of Patent: January 14, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry D. Bathan, Arnel Trasporto, Jeffrey D. Punzalan
  • Publication number: 20140011315
    Abstract: A semiconductor device is made by providing a semiconductor die having an optically active area, providing a leadframe or pre-molded laminated substrate having a plurality of contact pads and a light transmitting material disposed between the contact pads, attaching the semiconductor die to the leadframe so that the optically active area is aligned with the light transmitting material to provide a light transmission path to the optically active area, and disposing an underfill material between the semiconductor die and leadframe. The light transmitting material includes an elevated area to prevent the underfill material from blocking the light transmission path. The elevated area includes a dam surrounding the light transmission path, an adhesive ring, or the light transmission path itself can be the elevated area. An adhesive ring can be disposed on the dam. A filler material can be disposed between the light transmitting material and contact pads.
    Type: Application
    Filed: September 9, 2013
    Publication date: January 9, 2014
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Zigmund R. Camacho, Henry D. Bathan, Lionel Chien Hui Tay, Arnel Senosa Trasporto
  • Publication number: 20130341789
    Abstract: A semiconductor device is made by forming solder bumps over a copper carrier. Solder capture indentations are formed in the copper carrier to receive the solder bumps. A semiconductor die is mounted to the copper carrier using a die attach adhesive. The semiconductor die has contact pads formed over its active surface. An encapsulant is deposited over the copper carrier, solder bumps, and semiconductor die. A portion of the encapsulant is removed to expose the solder bumps and contact pads. A conductive layer is formed over the encapsulant to connect the solder bumps and contact pads. The conductive layer operates as a redistribution layer to route electrical signals from the solder bumps to the contact pads. The copper carrier is removed. An insulating layer is formed over the conductive layer and encapsulant. A plurality of semiconductor devices can be stacked and electrically connected through the solder bumps.
    Type: Application
    Filed: August 27, 2013
    Publication date: December 26, 2013
    Applicant: STATS ChipPAC, Ltd.
    Inventors: Zigmund R. Camacho, Lionel Chien Hui Tay, Henry D. Bathan, Dioscoro A. Merilo, Jeffrey D. Punzalan
  • Patent number: 8586422
    Abstract: A semiconductor device is made by providing a semiconductor die having an optically active area, providing a leadframe or pre-molded laminated substrate having a plurality of contact pads and a light transmitting material disposed between the contact pads, attaching the semiconductor die to the leadframe so that the optically active area is aligned with the light transmitting material to provide a light transmission path to the optically active area, and disposing an underfill material between the semiconductor die and leadframe. The light transmitting material includes an elevated area to prevent the underfill material from blocking the light transmission path. The elevated area includes a dam surrounding the light transmission path, an adhesive ring, or the light transmission path itself can be the elevated area. An adhesive ring can be disposed on the dam. A filler material can be disposed between the light transmitting material and contact pads.
    Type: Grant
    Filed: March 13, 2012
    Date of Patent: November 19, 2013
    Assignee: STATS ChipPAC, Ltd.
    Inventors: Zigmund R Camacho, Henry D Bathan, Lionel Chien Hui Tay, Amel Senosa Trasporto