Patents by Inventor Henry D. Bathan

Henry D. Bathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Integrated circuit package system with heat sink
    Patent number: 7400049
    Abstract: An integrated circuit package system is provided forming an external interconnect from a padless lead frame, encapsulating a heat sink and the external interconnect, mounting an integrated circuit die on the heat sink, and encapsulating the integrated circuit die, the heat sink, and the external interconnect.
    Type: Grant
    Filed: February 16, 2006
    Date of Patent: July 15, 2008
    Assignee: Stats Chippac Ltd.
    Inventors: Il Kwon Shim, Henry D. Bathan, Zigmund Ramirez Camacho, Jeffrey D. Punzalan
  • STACKABLE INTEGRATED CIRCUIT PACKAGE SYSTEM WITH RECESS
    Publication number: 20080157321
    Abstract: A stackable integrated circuit package system is provided including forming an external interconnect having an interconnect non-recessed portion and an interconnect recessed portion, mounting an integrated circuit die over a paddle that is coplanar with the interconnect recessed portion, and forming an encapsulation having a recess over the external interconnect and the integrated circuit die with the external interconnect exposed at a side of the encapsulation.
    Type: Application
    Filed: December 30, 2006
    Publication date: July 3, 2008
    Inventors: Zigmund Ramirez Camacho, Henry D. Bathan, Jose Alvin Caparas, Lionel Chien Hui Tay
  • INTEGRATED CIRCUIT PACKAGE WITH ELEVATED EDGE LEADFRAME
    Publication number: 20080142934
    Abstract: An integrated circuit package system includes an elevated edge leadframe array, isolating leadframes of the elevated edge leadframe array, validating integrated circuit die attached to the leadframes, and forming integrated circuit packages including the integrated circuit die.
    Type: Application
    Filed: December 13, 2006
    Publication date: June 19, 2008
    Applicant: STATS CHIPPAC LTD.
    Inventors: Zigmund Ramirez Camacho, Henry D. Bathan, Jose Alvin Caparas, Jeffrey D. Punzalan
  • INTEGRATED CIRCUIT PACKAGE SYSTEM WITH HEAT SINK
    Publication number: 20080111217
    Abstract: An integrated circuit package system is provided including forming a paddle, forming a ring with a recess in the paddle, mounting a device in the recess, forming a slot in the ring, and mounting a heat sink in the slot over the device.
    Type: Application
    Filed: November 9, 2006
    Publication date: May 15, 2008
    Applicant: STATS ChipPAC Ltd.
    Inventors: Antonio B. Dimaano, Il Kwon Shim, Henry D. Bathan, Jeffrey D. Punzalan
  • INTEGRATED CIRCUIT PACKAGE SYSTEM
    Publication number: 20080111215
    Abstract: An integrated circuit package system is provided including forming an external interconnect having a lead body and a lead tip, forming a lead protrusion in the lead tip, connecting a device and the external interconnect, and encapsulating the device and the external interconnect.
    Type: Application
    Filed: November 10, 2006
    Publication date: May 15, 2008
    Applicant: STATS ChipPAC Ltd.
    Inventors: Il Kwon Shim, Antonio B. Dimaano, Henry D. Bathan, Jeffrey D. Punzalan
  • Overhang integrated circuit package system
    Patent number: 7365417
    Abstract: An integrated circuit package system is provided attaching a film to a die paddle, applying an adhesive to the film, and attaching an integrated circuit die over the adhesive and the film to the die paddle.
    Type: Grant
    Filed: January 6, 2006
    Date of Patent: April 29, 2008
    Assignee: Stats Chippac Ltd.
    Inventors: Zigmund Ramirez Camacho, Henry D. Bathan, Arnel Trasporto, Jeffrey D. Punzalan
  • INTEGRATED CIRCUIT PACKAGE SYSTEM WITH LAMINATE BASE
    Publication number: 20080017960
    Abstract: An integrated circuit package system with laminate base is provided including forming a base package including, forming a laminate substrate strip, mounting an integrated circuit on the laminate substrate strip, forming a molded cover over the integrated circuit and the laminate substrate strip, and performing a strip test of the base package; attaching a bare die to the base package; connecting electrically the bare die to the laminate substrate strip; and encapsulating the bare die and the base package.
    Type: Application
    Filed: July 21, 2006
    Publication date: January 24, 2008
    Applicant: STATS CHIPPAC LTD.
    Inventors: Zigmund Ramirez Camacho, Henry D. Bathan, Arnel Trasporto, Jeffrey D. Punzalan
  • INTEGRATED CIRCUIT PACKAGE SYSTEM WITH FLASHLESS LEADS
    Publication number: 20080012100
    Abstract: An integrated circuit package system is provided including forming a lead frame including forming an inner lead having a planar surface, the inner lead extending inwardly from the lead frame and forming a stiffening structure integral with the lead frame for maintaining the planar surface; encapsulating the inner lead with an electrical connection to an integrated circuit die and with a first inner lead body of the inner lead exposed; and singulating the inner lead from the lead frame.
    Type: Application
    Filed: February 2, 2007
    Publication date: January 17, 2008
    Inventors: Jeffrey D. Punzalan, Henry D. Bathan, Il Kwon Shim, Zigmund Ramirez Camacho
  • INTEGRATED CIRCUIT PACKAGE SYSTEM WITH STIFFENER
    Publication number: 20080006926
    Abstract: An integrated circuit package system is provided including forming a mounting structure having an external interconnect, a paddle, and a tie bar; mounting an integrated circuit die on the paddle; soldering a stiffener structure; having an opening; on the mounting structure; connecting the stiffener structure to a ground; and molding the integrated circuit die and partially the stiffener structure through the opening.
    Type: Application
    Filed: July 10, 2006
    Publication date: January 10, 2008
    Applicant: STATS CHIPPAC LTD.
    Inventors: Henry D. Bathan, Antonio B. Dimaano, Jeffrey D. Punzalan, Zigmund Ramirez Camacho
  • Integrated circuit package system with adhesive restraint
    Patent number: 7274089
    Abstract: An integrated circuit package system including an integrated circuit die and a lead frame with a trenched die pad. The integrated circuit die is mounted to the trenched die pad.
    Type: Grant
    Filed: September 19, 2005
    Date of Patent: September 25, 2007
    Assignee: Stats Chippac Ltd.
    Inventors: Jeffrey D. Punzalan, Il Kwon Shim, Zigmund Ramirez Camacho, Henry D. Bathan
  • INTEGRATED CIRCUIT PACKAGE SYSTEM
    Publication number: 20070170559
    Abstract: An integrated circuit package system is provided forming a lead finger from a padless lead frame, forming a lead tip hole in the lead finger, mounting an integrated circuit die having a solder bump on the lead finger, and reflowing the solder bump on the lead tip hole of the lead finger.
    Type: Application
    Filed: January 24, 2006
    Publication date: July 26, 2007
    Applicant: STATS CHIPPAC LTD.
    Inventors: Zigmund Ramirez Camacho, Henry D. Bathan, Arnel Trasporto, Jeffrey D. Punzalan
  • System for semiconductor package with stacked dies
    Patent number: 6833287
    Abstract: A semiconductor package with stacked dies and method of assembly is provided. A first die is attached to a substrate. A protective layer is placed on the first die over a central area thereof. The first die is electrically connected to the substrate. An intermediate adhesive layer is applied over the protective layer. A second die is attached to the intermediate adhesive layer and electrically connected to the substrate.
    Type: Grant
    Filed: June 16, 2003
    Date of Patent: December 21, 2004
    Assignee: ST Assembly Test Services Inc.
    Inventors: Hyeong Ryeol Hur, Henry D. Bathan, Zigmund R. Camacho
  • SYSTEM FOR SEMICONDUCTOR PACKAGE WITH STACKED DIES
    Publication number: 20040251526
    Abstract: A semiconductor package with stacked dies and method of assembly is provided. A first die is attached to a substrate. A protective layer is placed on the first die over a central area thereof. The first die is electrically connected to the substrate. An intermediate adhesive layer is applied over the protective layer. A second die is attached to the intermediate adhesive layer and electrically connected to the substrate.
    Type: Application
    Filed: June 16, 2003
    Publication date: December 16, 2004
    Applicant: ST ASSEMBLY TEST SERVICES LTD.
    Inventors: Hyeong Ryeol Hur, Henry D. Bathan, Zigmund R. Camacho