Abstract: Control and feature systems for processing signals from a satellite positioning system include an expert system receiver manager; a joint detection, carrier centring and bit sync acquisition subsystem; peak detection; a multi-dimensional measurement interpolation subsystem; a system for mode switching between a navigational signal; and power control module for receiver.

Abstract: Control and feature systems for processing signals from a satellite positioning system include an expert system receiver manager; a joint detection, carrier centring and bit sync acquisition subsystem; peak detection; a multi-dimensional measurement interpolation subsystem; a system for mode switching between a navigational signal; and power control module for receiver.

Abstract: Control and feature systems for processing signals from a satellite positioning system include an expert system receiver manager; a joint detection, carrier centering and bit sync acquisition subsystem; peak detection; a multi-dimensional measurement interpolation subsystem; a system for mode switching between a navigational signal; and power control module for receiver.

Abstract: A signal processing system for processing satellite positioning signals is described. The system comprises at least one processor and a signal processor operating under a number of operational modes. The signal processor includes at least one of a signal processing subsystem, a fast Fourier transform (FFT) subsystem, and a memory subsystem that are each dynamically and independently configurable in response to the operational modes. Further, the system includes a controller that couples to control transfer of data among the signal processing subsystem and the FFT subsystem via the memory subsystem. Configurability of the memory subsystem includes configuring the memory subsystem into regions according to the operational modes where each region is accessible in one of a number of manners according to the operational modes.

Abstract: A signal processing system for processing satellite positioning signals is described. The system comprises at least one processor and a signal processor operating under a number of operational modes. The signal processor includes at least one of a signal processing subsystem, a fast Fourier transform (FFT) subsystem, and a memory subsystem that are each dynamically and independently configurable in response to the operational modes. Further, the system includes a controller that couples to control transfer of data among the signal processing subsystem and the FFT subsystem via the memory subsystem. Configurability of the memory subsystem includes configuring the memory subsystem into regions according to the operational modes where each region is accessible in one of a number of manners according to the operational modes.

Abstract: A signal processing system for processing satellite positioning signals is described. The system comprises at least one processor and a signal processor operating under a number of operational modes. The signal processor includes at least one of a signal processing subsystem, a fast Fourier transform (FFT) subsystem, and a memory subsystem that are each dynamically and independently configurable in response to the operational modes. Further, the system includes a controller that couples to control transfer of data among the signal processing subsystem and the FFT subsystem via the memory subsystem. Configurability of the memory subsystem includes configuring the memory subsystem into regions according to the operational modes where each region is accessible in one of a number of manners according to the operational modes.

Abstract: Control and feature systems for processing signals from a satellite positioning system include an expert system receiver manager; a joint detection, carrier centering and bit sync acquisition subsystem; peak detection; a multi-dimensional measurement interpolation subsystem; a system for mode switching between a navigational signal; and power control module for receiver.

Abstract: A shared memory architecture for a GPS receiver, wherein a processing memory is shared among the different processing functions, such as the correlator signal processing, tracking processing, and other applications processing. The shared memory architecture within the GPS receiver provides the memory necessary for signal processing operations, such as the massively parallel processing, while conserving memory cost by re-using that same memory for other GPS and non-GPS applications. The shared memory architecture for a GPS receiver provided in accordance with the principles of this invention thereby significantly minimize the costly memory requirement often required of extremely fast signal acquisition of a GPS receiver.

Abstract: Control and feature systems for processing signals from a satellite positioning system include an expert system receiver manager; a joint detection, carrier centering and bit sync acquisition subsystem; peak detection; a multi-dimensional measurement interpolation subsystem; a subsystem for mode switching between a navigational signal; and power control module for a receiver.

Abstract: A signal processing system for processing satellite positioning signals is described. The system comprises at least one processor and a signal processor operating under a number of operational modes. The signal processor includes at last one of a signal processing subsystem, a fast Fourier transform (FFT) subsystem, and a memory subsystem that are each dynamically and independently configurable in response to the operational modes. Further, the system includes a controller that couples to control transfer of data among the signal processing subsystem and the FFT subsystem via the memory subsystem. Configurability of the memory subsystem includes configuring the memory subsystem into regions according to the operational modes where each region is accessible in one of a number of manners according to the operational modes.

Abstract: The present invention discloses methods, apparatuses, and systems for eliminating auto- and cross-correlation in weak signal CDMA systems, such as GPS systems. The invention uses parallel data paths that allow standard correlation of signals in parallel with verification of the lock signal to determine whether the system has locked onto the proper signal within the scanned signal window. The invention can be made with multiple CPUs, a single CPU with dual input modes, on multiple IC chips, or as a single IC chip solution for small, low cost reception, downconversion, correlation, and verification systems.

Abstract: The present invention discloses methods, apparatuses, and systems for eliminating auto- and cross-correlation in weak signal CDMA systems, such as GPS systems. The invention uses parallel data paths that allow standard correlation of signals in parallel with verification of the lock signal to determine whether the system has locked onto the proper signal within the scanned signal window. The invention can be made with multiple CPUs, a single CPU with dual input modes, on multiple IC chips, or as a single IC chip solution for small, low cost reception, downconversion, correlation, and verification systems.

Abstract: Control and feature systems for processing signals from a satellite positioning system include an expert system receiver manager; a joint detection, carrier centering and bit sync acquisition subsystem; peak detection; a multi-dimensional measurement interpolation subsystem; a subsystem for mode switching between a navigational signal; and power control module for a receiver.

Abstract: The present invention discloses methods, apparatuses, and systems for eliminating auto- and cross-correlation in weak signal CDMA systems, such as GPS systems. The invention uses parallel data paths that allow standard correlation of signals in parallel with verification of the lock signal to determine whether the system has locked onto the proper signal within the scanned signal window. The invention can be made with multiple CPUs, a single CPU with dual input modes, on multiple IC chips, or as a single IC chip solution for small, low cost reception, downconversion, correlation, and verification systems.

Abstract: The present invention discloses methods, apparatuses, and systems for eliminating auto- and cross-correlation in weak signal CDMA systems, such as GPS systems. The invention uses parallel data paths that allow standard correlation of signals in parallel with verification of the lock signal to determine whether the system has locked onto the proper signal within the scanned signal window. The invention can be made with multiple CPUs, a single CPU with dual input modes, on multiple IC chips, or as a single IC chip solution for small, low cost reception, downconversion, correlation, and verification systems.

Abstract: The present invention discloses methods, apparatuses, and systems for eliminating auto- and cross-correlation in weak signal CDMA systems, such as GPS systems. The invention uses parallel data paths that allow standard correlation of signals in parallel with verification of the lock signal to determine whether the system has locked onto the proper signal within the scanned signal window. The invention can be made with multiple CPUs, a single CPU with dual input modes, on multiple IC chips, or as a single IC chip solution for small, low cost reception, downconversion, correlation, and verification systems.

Abstract: The present invention discloses methods, apparatuses, and systems for eliminating auto- and cross-correlation in weak signal CDMA systems, such as GPS systems. The invention uses parallel data paths that allow standard correlation of signals in parallel with verification of the lock signal to determine whether the system has locked onto the proper signal within the scanned signal window. The invention can be made with multiple CPUs, a single CPU with dual input modes, on multiple IC chips, or as a single IC chip solution for small, low cost reception, downconversion, correlation, and verification systems.

Abstract: The present invention discloses methods, apparatuses, and systems for eliminating auto- and cross-correlation in weak signal CDMA systems, such as GPS systems. The invention uses parallel dam paths that allow standard correlation of signals in parallel with verification of the lock signal to determine whether the system has locked onto the proper signal within the scanned signal window. The invention can be made with multiple CPUs, a single CPU with dual input modes, on multiple IC chips, or as a single IC chip solution for small, low cost reception, downconversion, correlation, and verification systems.

Abstract: A shared memory architecture for a GPS receiver, wherein a processing memory is shared among the different processing functions, such as the correlator signal processing, tracking processing, and other applications processing. The shared memory architecture within the GPS receiver provides the memory necessary for signal processing operations, such as the massively parallel processing, while conserving memory cost by re-using that same memory for other GPS and non-GPS applications. The shared memory architecture for a GPS receiver provided in accordance with the principles of this invention thereby significantly minimize the costly memory requirement often required of extremely fast signal acquisition of a GPS receiver.

Abstract: The present invention discloses methods, apparatuses, and systems for eliminating auto- and cross-correlation in weak signal CDMA systems, such as GPS systems. The invention uses parallel dam paths that allow standard correlation of signals in parallel with verification of the lock signal to determine whether the system has locked onto the proper signal within the scanned signal window. The invention can be made with multiple CPUs, a single CPU with dual input modes, on multiple IC chips, or as a single IC chip solution for small, low cost reception, downconversion, correlation, and verification systems.